Assuring Comprehensive Security Coverage In Hardware Design


Is your hardware design prepared to withstand today’s complex threat landscape? Verifying the effectiveness of security functionality and protections is essential to safeguarding your designs. By adopting a systematic framework and measuring coverage throughout the pre-silicon development cycle, you can proactively identify vulnerabilities and strengthen your hardware’s resilience. Downl... » read more

Leveraging Agentic AI Techniques to Improve Formal Verification (Infineon, et al.)


A new technical paper, "Agentic AI-based Coverage Closure for Formal Verification," was published by researchers at Infineon and the NIT Jalandhar. Abstract "Coverage closure is a critical requirement in Integrated Chip (IC) development process and key metric for verification sign-off. However, traditional exhaustive approaches often fail to achieve full coverage within project timelines.... » read more

LLM- Based Techniques To Support Behavior-Driven Development For HW Design (U. of Bremen, DFKI)


A new technical paper titled "LLM-based Behaviour Driven Development for Hardware Design" was published by researchers at University of Bremen/DFKI. Abstract "Test and verification are essential activities in hardware and system design, but their complexity grows significantly with increasing system sizes. While Behavior Driven Development (BDD) has proven effective in software engineerin... » read more

IP And Data Management: Challenges, Solutions, And Best-in-Class Approaches


As electronic design becomes increasingly complex, traditional approaches to IP and design data management are reaching their limits. Fragmented systems, inconsistent documentation, and unclear version control are slowing collaboration, increasing rework, and ultimately constraining innovation. The ability to manage design data effectively is no longer a background concern — it’s a foundati... » read more

Identifying Divergences in HW Designs For High Performance Computing Workloads (LBNL et al.)


A new technical paper titled "Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads" was published by Lawrence Berkeley National Lab (LBNL), Foundation for Research and Technology - Hellas and University of Houston Clear Lake. Abstract "Developing efficient hardware accelerators for mathematical kernels used in scientific applications and machine learning has tra... » read more

Overview of Incorporating LLMs into EDA, With 3 Case Studies (TU Munich et al.)


A new technical paper titled "Large Language Models (LLMs) for Electronic Design Automation (EDA)" was published by researchers at the Technical University of Munich, University of Stuttgart, New York University, and University of Siegen. Abstract "With the growing complexity of modern integrated circuits, hardware engineers are required to devote more effort to the full design-to-manufactu... » read more

PCB Modularity Reuse and Scale


In a world of shrinking timelines and growing complexity, modularity isn't a luxury—it's a necessity. This eBook explores how PCB designers can move from one-off designs to scalable systems by rethinking schematics, embracing abstraction, and designing for reuse. What you’ll learn: How modular thinking drives scalability Why abstraction accelerates hardware design How to ap... » read more

Survey: HW SW Co-Design Approaches Tailored to LLMs


A new technical paper titled "A Survey: Collaborative Hardware and Software Design in the Era of Large Language Models" was published by researchers at Duke University and Johns Hopkins University. Abstract "The rapid development of large language models (LLMs) has significantly transformed the field of artificial intelligence, demonstrating remarkable capabilities in natural language proce... » read more

LLMs In The High-Level Synthesis Design Flow


A new technical paper titled "Are LLMs Any Good for High-Level Synthesis?" was published by researchers at University of Arizona. Abstract "The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS proces... » read more

LLMs For EDA, HW Design and Security


A new technical paper titled "Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge" was published by researchers at Kansas State University, University of Science and Technology of China, Michigan Technological University, Washington University in St. Louis and Silicon Assurance. Abstract "In the rapidly evolving semiconductor industry, where research, design... » read more

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