Rowhammer Exploitation On AMD Platforms, DDR4 DDR5 (ETH Zurich)


A new technical paper titled "ZenHammer: Rowhammer Attacks on AMD Zen-based Platforms" was published by researchers at ETH Zurich. The work will be presented at USENIX Security Symposium in August 2024. Abstract: "AMD has gained a significant market share in recent years with the introduction of the Zen microarchitecture. While there are many recent Rowhammer attacks launched from Intel CPU... » read more

New Memory Architecture For Local Differential Privacy in Hardware


A technical paper titled "Two Birds with One Stone: Differential Privacy by Low-power SRAM Memory" was published by researchers at North Carolina State University, University of South Alabama, and University of Tennessee. Abstract "The software-based implementation of differential privacy mechanisms has been shown to be neither friendly for lightweight devices nor secure against side-channe... » read more

Verifying Hardware CWEs in RTL Designs Generated by GenAI


A new technical paper titled "All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification" was published by researchers at Infineon Technologies. Abstract "Modern hardware designs have grown increasingly efficient and complex. However, they are often susceptible to Common Weakness Enumerations (CWEs). This paper is focused on the formal verification of CWEs in a dataset... » read more

Hardware Trojans: CPU-Oriented Trojan Trigger Circuits (Georgia Tech)


A new technical paper titled "Towards Practical Fabrication Stage Attacks Using Interrupt-Resilient Hardware Trojans" was published by researchers at Georgia Tech. The paper states: "We introduce a new class of hardware trojans called interrupt-resilient trojans (IRTs). Our work is motivated by the observation that hardware trojan attacks on CPUs, even under favorable attack scenarios (e.g.... » read more

Suppressing Power Side-Channel Attacks: A HW/SW Design For Resource-Constrained IoT Devices


A technical paper titled “Hardware/Software Cooperative Design Against Power Side-Channel Attacks on IoT Devices” was published by researchers at Tokyo Institute of Technology and the University of Electro-Communications. Abstract: "With the growth of Internet of Things (IoT) era, the protection of secret information on IoT devices is becoming increasingly important. For IoT devices, atta... » read more

K-Fault Resistant Partitioning To Assess Redundancy-Based HW Countermeasures To Fault Injections


A technical paper titled “Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults” was published by researchers at Université Paris-Saclay, Graz University of Technology, lowRISC, University Grenoble Alpes, Thales, and Sorbonne University. Abstract: "To assess the robustness of CPU-based systems against fault injection attacks, it is necessary to analyze the... » read more

An Analytical EM Model For IC Shielding Against HW Attacks


A technical paper titled “Refined Analytical EM Model of IC-Internal Shielding for Hardware-Security and Intra-Device Simulative Framework” was published by researchers at Bar-Ilan University and Rafael Defense Systems. Abstract: "Over the past two decades, the prominence of physical attacks on electronic devices, designed to extract confidential information, has surged. These attacks exp... » read more

Broad Impact From Accelerating Tech Cycles


Experts at the Table: Semiconductor Engineering sat down to discuss the impact of leading edge technologies such as generative AI in data centers, AR/VR, and security architectures for connected devices, with Michael Kurniawan, business strategy manager at Accenture; Kaushal Vora, senior director and head of business acceleration and ecosystem at Renesas Electronics; Paul Karazuba, vice preside... » read more

HW Security Bug Characteristics in Google’s OpenTitan Silicon Root Of Trust Project 


A technical paper titled “An Investigation of Hardware Security Bug Characteristics in Open-Source Projects” was published by researchers at NYU Tandon School of Engineering and University of Calgary. Abstract: "Hardware security is an important concern of system security as vulnerabilities can arise from design errors introduced throughout the development lifecycle. Recent works have pro... » read more

Radix Coverage for Hardware Common Weakness Enumeration (CWE) Guide (updated)


MITRE’s hardware Common Weakness Enumeration (CWE) database aggregates hardware weaknesses that are the root causes of vulnerabilities in deployed parts. In this 100+ page guide, each CWE is listed along with a Radix template Security Rule that can be filled in with design-specific signals and used as a baseline test for the respective CWE. To learn more about a specific CWE, follow the li... » read more

← Older posts Newer posts →