Broad Impact From Accelerating Tech Cycles


Experts at the Table: Semiconductor Engineering sat down to discuss the impact of leading edge technologies such as generative AI in data centers, AR/VR, and security architectures for connected devices, with Michael Kurniawan, business strategy manager at Accenture; Kaushal Vora, senior director and head of business acceleration and ecosystem at Renesas Electronics; Paul Karazuba, vice preside... » read more

HW Security Bug Characteristics in Google’s OpenTitan Silicon Root Of Trust Project 


A technical paper titled “An Investigation of Hardware Security Bug Characteristics in Open-Source Projects” was published by researchers at NYU Tandon School of Engineering and University of Calgary. Abstract: "Hardware security is an important concern of system security as vulnerabilities can arise from design errors introduced throughout the development lifecycle. Recent works have pro... » read more

Radix Coverage for Hardware Common Weakness Enumeration (CWE) Guide (updated)


MITRE’s hardware Common Weakness Enumeration (CWE) database aggregates hardware weaknesses that are the root causes of vulnerabilities in deployed parts. In this 100+ page guide, each CWE is listed along with a Radix template Security Rule that can be filled in with design-specific signals and used as a baseline test for the respective CWE. To learn more about a specific CWE, follow the li... » read more

How To Stop Row Hammer Attacks


Row hammer is a well-publicized target for cyberattacks on DRAM, and there have been attempts to stop these attacks in DDR4 and DDR5, but with mixed results. The problem is that as density increases, distance decreases, making it more likely that flipped bit cell in one row can disturb a bit cell in another, and that bits flipped across an entire row can flip another row. Steven Woo, fellow and... » read more

Challenges And Innovations Of HW Security And Trust For Chiplet-Based 2.5D and 3D ICs


A technical paper titled “On hardware security and trust for chiplet-based 2.5D and 3D ICs: Challenges and Innovations” was published by researchers at STMicroelectronics Crolles (ST-CROLLES), Département Systèmes et Circuits Intégrés Numériques (DSCIN), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Laboratoire Systèm... » read more

SystemC-based Power Side-Channel Attacks Against AI Accelerators (Univ. of Lubeck)


A new technical paper titled "SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?" was published by researchers at Germany's University of Lubeck. Abstract "As training artificial intelligence (AI) models is a lengthy and hence costly process, leakage of such a model's internal parameters is highly undesirable. In the case of AI accelerators, side-chann... » read more

Nanoscale Reconfigurable Si Transistors (TU Wien, CNRS, UNC)


A new technical paper titled "Nanoscale Reconfigurable Si Transistors: From Wires to Sheets and Unto Multi-Wire Channels" was published by researchers at TU Wien, CNRS, and University of North Carolina at Chapel Hill. Abstract: "In this work, bottom-up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top-down fabricated nanosheet (NS) and ... » read more

Hardware-Based Methodology To Protect AI Accelerators


A technical paper titled “A Unified Hardware-based Threat Detector for AI Accelerators” was published by researchers at Nanyang Technological University and Tsinghua University. Abstract: "The proliferation of AI technology gives rise to a variety of security threats, which significantly compromise the confidentiality and integrity of AI models and applications. Existing software-based so... » read more

More Efficient Side-Channel Analysis By Applying Two Deep Feature Loss Functions


A technical paper titled “Beyond the Last Layer: Deep Feature Loss Functions in Side-channel Analysis” was published by researchers at Nanyang Technological University, Radboud University, and Delft University of Technology. Abstract: "This paper provides a novel perspective on improving the efficiency of side-channel analysis by applying two deep feature loss functions: Soft Nearest Neig... » read more

Hardware Fuzzing With MAB Algorithms


A technical paper titled “MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors” was published by researchers at Texas A&M University and Technische Universitat Darmstadt. Abstract: "As the complexities of processors keep increasing, the task of effectively verifying their integrity and security becomes ever more daunting. The intricate web of instructions, microarchitectural ... » read more

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