tag: HCI

Chip Aging Becomes Design Problem
By Brian Bailey - 09 Aug, 2018 - Comments: 9

Chip aging is a growing problem at advanced nodes, but so far most design teams have not had to deal with it. That will change significantly as new reliability requirements roll out across markets such as automotive, which require a complete analysis of factors that affect aging. Understanding the underlying physics is critical, because it can lead to unexpected results and vulnerabilities. ... » read more

Multiphysics Reliability Signoff For Next-Gen Auto Electronics Systems
By Annapoorna Krishnaswamy - 12 Mar, 2018 - Comments: 0

The automotive industry is in the midst of a sea change. Growing market needs for electrification, connectivity on the go, advanced driver assistance systems, and ultimately the goal of autonomous driving, are creating newer requirements and greater challenges. A chassis on four wheels is now fitted with cameras, radar and other sensors, which will be the eyes of the driverless car, as well as ... » read more

Transistor Aging Intensifies At 10/7nm And Below
By Ann Mutschler - 13 Jul, 2017 - Comments: 0

Transistor aging and reliability are becoming much more troublesome for design teams at 10nm and below. Concepts like ‘infant mortality’ and 'bathtub curves' are not new to semiconductor design, but they largely dropped out of sight as methodologies and EDA tools improved. To get past infant mortality, a burn-in process would be done, particularly for memories. And for reliability, which... » read more

Improving Transistor Reliability
By Katherine Derbyshire - 21 Apr, 2016 - Comments: 1

One of the more important challenges in reliability testing and simulation is the duty cycle dependence of degradation mechanisms such as negative bias temperature instability ([getkc id="278" kc_name="NBTI"]) and hot carrier injection (HCI). For example, as previously discussed, both the shift due to NBTI and the recovery of baseline behavior are very dependent on device workload. This is ... » read more

Transistor-Level Verification Returns
By Brian Bailey - 13 Jan, 2016 - Comments: 1

A few decades ago, all designers did transistor-level verification, but they were quite happy to say goodbye to it when standard cells provided isolation at the gate-level and libraries provided all of the detailed information required, such as timing. A few dedicated people continued to use the technology to provide those models and libraries and the most aggressive designs that wanted to stri... » read more

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