Bespoke Silicon Rattles Chip Design Ecosystem

By Ann Mutschler - 19 Oct, 2022 - Comments: 0

Bespoke silicon developers are shaking up relationships, priorities, and methodologies across the semiconductor industry, creating demand for skills that cross traditional boundaries, and driving new business models that leverage these enormous investments. Bespoke silicon designers today are a rare breed, capable of understanding the unique requirements of a specific domain, as well as a gr... » read more

Week In Review: Design, Low Power

By Jesse Allen - 13 Sep, 2019 - Comments: 0

M&A ANSYS will acquire Livermore Software Technology Corp. (LSTC), a provider of explicit dynamics and other advanced finite element analysis technology. Based in Livermore, CA, LSTC was founded in 1987 to commercialize the DYNA3D technology developed at the Lawrence Livermore National Laboratory. DYNA3D became the company's premier product LS-DYNA, a general purpose nonlinear finite eleme... » read more

The Week In Review: IoT

By Jeff Dorsch - 25 Nov, 2016 - Comments: 0

Analysis The Internet of Things may be entering the infamous “Trough of Disillusionment” in the Gartner Hype Cycle, according to some observers. “There’s a general malaise growing around IoT. Where is this shiny, artificially intelligent, fully connected future of things we were promised?” iobeam CEO Ajay Kulkarni writes in this analysis. Others are more sanguine about the IoT. Clear... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: HCL Technologies

Bespoke Silicon Rattles Chip Design Ecosystem

Week In Review: Design, Low Power

The Week In Review: IoT