Chip Industry Week In Review

By The SE Staff - 29 Sep, 2023 - Comments: 0

By Susan Rambo, Liz Allan, and Gregory Haley. TSMC rolled out the second version of its 3Dblox, which creates an infrastructure for stacking chiplets and other necessary components in a package, along with a standardized way of achieving that. Two novel features are chiplet mirroring for design reuse, and what is basically sandbox for power and thermal analysis of different design elements. ... » read more

Week In Review: Design, Low Power

By Jesse Allen - 01 Apr, 2022 - Comments: 0

Tools Synopsys introduced a new model for using its EDA tools on the cloud. Synopsys Cloud provides pay-as-you-go access to the company's cloud-optimized design and verification products, with pre-optimized infrastructure on Microsoft Azure to address higher levels of interdependencies in chip development. "As more design flows incorporate AI, requiring even more resources, the virtually unlim... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 01 Apr, 2022 - Comments: 0

Automotive Verizon and Cisco demonstrated a C-V2X network for autonomous driving in Las Vegas that avoids using costly physical roadside units to extend radio signals. Instead, Verizon and Cisco say their test proved that Verizon’s LTE network and public 5G Edge with AWS Wavelength, together with Cisco Catalyst IR1101 routers in connected infrastructure, were adequate to meet the latency nee... » read more

Week In Review: Design, Low Power

By Jesse Allen - 23 Aug, 2019 - Comments: 0

Xilinx debuted the Virtex UltraScale+ VU19P, which the company says is now the world's largest FPGA at 1.6X the size of its predecessor. The VU19P features 35 billion transistors, 9 million system logic cells, up to 1.5 terabits per-second of DDR4 memory bandwidth and up to 4.5 terabits per-second of transceiver bandwidth, and over 2,000 user I/Os. With a set of debug, visibility tools, and IP,... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: HDL Design House

Chip Industry Week In Review

Week In Review: Design, Low Power

Week In Review: Auto, Security, Pervasive Computing

Week In Review: Design, Low Power