Package Assembly Design Kits (PADK) Benefits For Packaging Design Engineers

By Amkor - 21 Nov, 2024 - Comments: 0

A new IEEE technical paper titled "Package Assembly Design Kits (PADK's)- The Future of Advanced Wafer-Level Manufacturing" was written by researchers from Amkor. Find the technical paper here. September 2024. "Although package design and IC design are two different worlds, they share several key similarities that have contributed to the successful use of Package Assembly Design Kits (PAD... » read more

Revolutionizing IC Packaging With High-Density RDL Technology

By Curtis Zwenger - 24 Oct, 2024 - Comments: 0

The demand for high-performance devices, particularly in AI, HPC, and data centers, has surged dramatically in the ever-evolving landscape of integrated circuit technology. This demand has been further accelerated by the COVID-19 pandemic, pushing the boundaries of silicon technology to its limits. Enter Amkor’s S-SWIFT, a packaging solution designed to address these challenges and revolution... » read more

Package Assembly Design Kits: The Future Of Advanced Package Design

By Ruben Fuentes - 23 May, 2024 - Comments: 0

Why should there be an interest in Package Assembly Design Kits (PADK) today? For the most part, it is due to the advancement in the accumulation of files forming the PADK now offering a customized heterogeneous design experience that optimizes the device's intended package performance with complete connectivity verification, DRC, and assembly validation. Another primary reason is the ongoing f... » read more

Electromigration Concerns Grow In Advanced Packages

By Laura Peters - 18 Apr, 2024 - Comments: 0

The incessant demand for more speed in chips requires forcing more energy through ever-smaller devices, increasing current density and threatening long-term chip reliability. While this problem is well understood, it's becoming more difficult to contain in leading-edge designs. Of particular concern is electromigration, which is becoming more troublesome in advanced packages with multiple ch... » read more

Electromigration Performance Of Fine-Line Cu Redistribution Layer (RDL) For HDFO Packaging

By JiHye Kwon - 18 Jan, 2024 - Comments: 1

The downsizing trend of devices gives rise to continuous demands of increasing input/output (I/O) and circuit density, and these needs encourage the development of a High-Density Fan-Out (HDFO) package with fine copper (Cu) redistribution layer (RDL). For mobile and networking application with high performance, HDFO is an emerging solution because aggressive design rules can be applied to HDFO ... » read more

High-Density Fan-Out Packaging With Fine Pitch Embedded Trace RDL

By WonChul Do - 15 Jun, 2023 - Comments: 0

The needs of high-performance devices for artificial intelligence (AI), high performance computing (HPC) and data center applications have drastically accelerated during the Covid-19 pandemic period. At the same time, the integrated circuit (IC) industry struggles to minimize the silicon technology node to satisfy the endless requirements of computing performance within tight cost constraints. ... » read more

Thermal Simulation Of DSMBGA And Coupled Thermal-Mechanical Simulation Of Large Body HDFO

By Nathan Whitchurch - 15 Sep, 2022 - Comments: 0

Electronic packaging has continued to become more complex with higher device count, higher power densities and Heterogeneous Integration (HI) becoming more common. In the mobile space, systems that were once separate components on a printed circuit board (PCB) have now been relocated along with all their associated passive devices and interconnects into single System in Package (SiP) style suba... » read more

Wafer Level Void-Free Molded Underfill For High-Density Fan-out Packages

By Amkor - 18 May, 2022 - Comments: 0

In this study, experiments and mold flow simulation results are presented for a void-free wafer level molded underfill (WLMUF) process with High-Density Fan-Out (HDFO) test vehicles using a wafer-level compression molding process. The redistribution layer (RDL)-first technology was applied with 3 layers of a fine-pitch RDL structure. The test samples comprised 11.5 x 12.5-mm2 die with tall copp... » read more

Chip-Last HDFO (High-Density Fan-Out) Interposer-PoP

By Amkor - 17 Feb, 2022 - Comments: 0

Interposer Package-on-Package (PoP) technology was developed and has been in very high-volume production over the last several years for high-end mobile application processors (APs). This is due to its advantages of good package design flexibility, controllable package warpage at room temperature (25°C) and high temperature (260°C), reduced assembly manufacturing cycle time and chip-last asse... » read more

Future Challenges For Advanced Packaging

By Mark LaPedus - 20 Jan, 2022 - Comments: 1

Michael Kelly, vice president of advanced packaging development and integration at Amkor, sat down with Semiconductor Engineering to talk about advanced packaging and the challenges with the technology. What follows are excerpts of that discussion. SE: We’re in the midst of a huge semiconductor demand cycle. What’s driving that? Kelly: If you take a step back, our industry has always ... » read more

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