Fast and Flexible FPGA-based NoC Hybrid Emulation

Researchers from RWTH Aachen University and Otto-von-Guericke Universitat Magdeburg have published a new technical paper titled "EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs." Abstract: "Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs to edge-AI accelerators. Emulation on FPGAs promises to accelerate their RTL modeling co... » read more

Hybrid Emulation Takes Center Stage

From mobile to networking to AI applications, system complexity shows no sign of slowing. These designs, which may contain multiple billion gates, must be validated, verified and tested, and it’s no longer possible to just throw the whole thing in a hardware emulator. For some time, emulation, FPGA-based prototyping, and virtual environments such as simulators have given design and verific... » read more

Emulating Systems Of Systems

System design is all the craze these days. I have been in notably more discussions recently about how one can verify systems of systems. Does an airplane or a car lend itself to an array of emulators? Are multiple abstractions needed? How can design teams span electrical, mechanical, and thermal—as well as analog and digital—effects? Do companies need to re-organize to deal with system desi... » read more

Hybrid Emulation

Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Hardware Models For Software

Shift left, while a relatively new term, has become important in all parts of the SoC design flow, but its impacts are wide ranging and many still ill defined. It basically means that tasks have to be started earlier than in the past because more accuracy is required from tasks that are further down in the flow in order to make better predictions. It also implies that more steps are performed c... » read more

Stop Getting Burned By Power Consumption Surprises

Very rarely these days do we get silicon back and find that we have missed our timing or test constraints by a significant margin. We have robust EDA tools, libraries and design methodologies in place to ensure that we can cleanly signoff against these constraints. However, we do continue to see too many unfortunate “surprises” in silicon related power (energy) consumption and thermal issue... » read more

Say Hi To Hybrid

It has been proposed for some time that virtual platforms could be linked to emulation hardware in order to co-verify the software and hardware components of an SoC. However, that proposal now has evolved into hybrid emulation, a practical solution to allow pre-silicon verification and validation of today’s complex SoC designs. First-rate work by the standards body Accellera and the Open ... » read more

Shift Left: Software Or Hardware?

A couple of weeks ago I was with a virtual prototyping user who described the benefits his company has seen from deploying virtual prototyping for early software development. The use of virtual prototyping has been rolled out progressively to more projects over the years, making it possible for the company to measure its impact on the software availability schedule and the impact has been drama... » read more

Leveraging Virtual Prototypes For Hybrid Emulation

As highlighted in many of my blog posts, virtual prototyping has really established itself as the key methodology to shift left software development by decoupling the dependency of software development from hardware availability. The success of the “Better Software. Faster!” book illustrates the wide spread interest in the methodology. The success of virtual prototypes also has led users... » read more