NVMs: In-Memory Fine-Grained Integrity Verification Technique (Intel Labs, IISc)


A new technical paper titled "iMIV: in-Memory Integrity Verification for NVM" was published by researchers at Intel Labs and Indian Institute of Science (IISc), Bengaluru. Abstract "Non-volatile Memory (NVM) could bridge the gap between memory and storage. However, NVMs are susceptible to data remanence attacks. Thus, multiple security metadata must persist along with the data to protect th... » read more

A Memory Device With MoS2 Channel For High-Density 3D NAND Flash-Based In-Memory Computing


A technical paper titled “Low-Power Charge Trap Flash Memory with MoS2 Channel for High-Density In-Memory Computing" was published by researchers at Kyungpook National University, Sungkyunkwan University, Dankook University, and Kwangwoon University. Abstract: "With the rise of on-device artificial intelligence (AI) technology, the demand for in-memory computing has surged for data-intensiv... » read more

Research Bits: May 28


Nanofluidic memristive neural networks Engineers from EPFL developed a functional nanofluidic memristive device that relies on ions, rather than electrons and holes, to compute and store data. “Memristors have already been used to build electronic neural networks, but our goal is to build a nanofluidic neural network that takes advantage of changes in ion concentrations, similar to living... » read more

Ferroelectric Memory-Based IMC for ML Workloads


A new technical paper titled "Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads" was published by researchers at Purdue University. Abstract "This study discusses the feasibility of Ferroelectric Capacitors (FeCaps) and Ferroelectric Field-Effect Transistors (FeFETs) as In-Memory Computing (IMC) elements to accelerate mach... » read more

In-Memory Computing: Techniques for Error Detection and Correction


A new technical paper titled "Error Detection and Correction Codes for Safe In-Memory Computations" was published by researchers at Robert Bosch, Forschungszentrum Julich, and Newcastle University. Abstract "In-Memory Computing (IMC) introduces a new paradigm of computation that offers high efficiency in terms of latency and power consumption for AI accelerators. However, the non-idealities... » read more

Novel Neuromorphic Artificial Neural Network Circuit Architecture


A technical paper titled “Mosaic: in-memory computing and routing for small-world spike-based neuromorphic systems” was published by researchers at CEA-LETI Université Grenoble Alpes, University of Zurich and ETH Zurich. Abstract: "The brain’s connectivity is locally dense and globally sparse, forming a small-world graph—a principle prevalent in the evolution of various species, sugg... » read more

Ferroelectric Tunnel Junctions In Crossbar Array Analog In-Memory Compute Accelerators


A technical paper titled “Ferroelectric Tunnel Junction Memristors for In-Memory Computing Accelerators” was published by researchers at Lund University. Abstract: "Neuromorphic computing has seen great interest as leaps in artificial intelligence (AI) applications have exposed limitations due to heavy memory access, with the von Neumann computing architecture. The parallel in-memory comp... » read more

Large-Scale Integration Of 2D Materials As The Semiconducting Channel In An In-Memory Processor (EPFL)


A technical paper titled “A large-scale integrated vector-matrix multiplication processor based on monolayer molybdenum disulfide memories” was published by researchers at École Polytechnique Fédérale de Lausanne (EPFL). Abstract: "Data-driven algorithms—such as signal processing and artificial neural networks—are required to process and extract meaningful information from the mass... » read more

Stacked Ferroelectric Memory Array Comprised Of Laterally Gated Ferroelectric Field-Effect Transistors


A technical paper titled “Laterally gated ferroelectric field effect transistor (LG-FeFET) using α-In2Se3  for stacked in-memory computing array” was published by researchers at Samsung Electronics and Sungkyunkwan University. Abstract: "In-memory computing is an attractive alternative for handling data-intensive tasks as it employs parallel processing without the need for data transfe... » read more

FeFET Multi-Level Cells For In-Memory Computing In 28nm


A technical paper titled “First demonstration of in-memory computing crossbar using multi-level Cell FeFET” was published by researchers at Robert Bosch, University of Stuttgart, Indian Institute of Technology Kanpur, Fraunhofer IPMS, RPTU Kaiserslautern-Landau, and Technical University of Munich. Abstract: "Advancements in AI led to the emergence of in-memory-computing architectures as a... » read more

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