Luminary Panel Sees Progress In EUV Pellicle Adoption As Critical For EUV

By Jan Willis - 21 Nov, 2024 - Comments: 0

A significant focus of the 2024 SPIE Photomask and EUV conference was on EUV lithography and high-numerical-aperture (high-NA) EUV lithography, offering the potential to drive resolution to new heights. These EUV solutions bring new challenges such as pellicles, mask inspection, and smaller and smaller minimum mask dimensions. Progress has been impressive, according to lithography luminary Dr. ... » read more

Multi-Tier Die Stacking Enables Efficient Manufacturing

By Jessica Albright - 24 Oct, 2024 - Comments: 0

Advanced packaging is currently facing a critical challenge to increase manufacturing efficiency without sacrificing device performance. Vertical integration techniques, such as multi-tier die stacking and hybrid bonding, enable increased integration density, therefore improving yield of high-quality devices. However, these highly precise processes require significant attention to defectivity... » read more

The Long Climb: Bringing Through Glass Vias (TGV) To High-Volume Manufacturing

By Keith Best - 15 Oct, 2024 - Comments: 0

The semiconductor industry is a land of peaks and valleys. It’s a place where each innovation represents the culmination of a long and often difficult climb to the summit. In the case of glass substrates, the peak of the mountain is in sight. The arrival of glass substrates comes at an opportune time, as the industry eyes new process innovations to meet the incredible demand for high perfo... » read more

Metrology Advances Step Up To Sub-2nm Device Node Needs

By Laura Peters - 15 Oct, 2024 - Comments: 0

Metrology and inspection are dealing with a slew of issues tied to 3D measurements, buried defects, and higher sensitivity as device features continue to shrink to 2nm and below. This is made even more challenging due to increasing pressure to ramp new processes more quickly. Metrology tool suppliers must exceed current needs by a process node or two to ensure solutions are ready to meet tig... » read more

Metrology And Inspection For The Chiplet Era

By Gregory Haley - 06 Aug, 2024 - Comments: 0

New developments and innovations in metrology and inspection will enable chipmakers to identify and address defects faster and with greater accuracy than ever before, all of which will be required at future process nodes and in densely packed assemblies of chiplets. These advances will affect both front-end and back-end processes, providing increased precision and efficiency, combined with a... » read more

Driving Cost Lower and Power Higher With GaN

By Anne Meixner - 06 Aug, 2024 - Comments: 0

Gallium nitride is starting to make broader inroads in the lower-end of the high-voltage, wide-bandgap power FET market, where silicon carbide has been the technology of choice. This shift is driven by lower costs and processes that are more compatible with bulk silicon. Efficiency, power density (size), and cost are the three major concerns in power electronics, and GaN can meet all three c... » read more

Classification and Localization of Semiconductor Defect Classes in Aggressive Pitches (imec, Screen)

By Technical Paper Link - 01 Aug, 2024 - Comments: 0

A new technical paper titled "An Evaluation of Continual Learning for Advanced Node Semiconductor Defect Inspection" was published by Imec and SCREEN SPE Germany. Abstract "Deep learning-based semiconductor defect inspection has gained traction in recent years, offering a powerful and versatile approach that provides high accuracy, adaptability, and efficiency in detecting and classifying... » read more

Achieving Zero Defect Manufacturing Part 1: Detect & Classify

By Prasad Bachiraju - 11 Jun, 2024 - Comments: 0

Whether the discussion is about smart manufacturing or digital transformation, one of the biggest conversations in the semiconductor industry today centers on the tremendous amount of data fabs collect and how they utilize that data. While chip makers are accumulating petabytes of data across the entire semiconductor process, a question arises: how much of that information is being fully uti... » read more

A Wrap-Up Of Photomask Japan 2024

By Ingo Bork - 23 May, 2024 - Comments: 0

This year, I had the opportunity to attend the 30th Symposium on Photomask and NGL Mask Technology, also called Photomask Japan 2024 (PMJ), in Yokohama, Japan, from April 16 to 18. This well-regarded symposium brings together engineers from all over the world to share ideas on photomasks, NGL masks and related technologies. It was great being back to an in-person conference after four years ... » read more

Progress In Wafer And Package Level Defect Inspection

By Anne Meixner - 09 Apr, 2024 - Comments: 0

The technology to enable sampling and the need for more metrology and inspection data in a production setting have aligned just in time to address the semiconductor industry’s newest and most complex manufacturing processes. In both wafer and assembly manufacturing, engineering teams have long relied on imaging tools to measure critical features and to inspect for defects after specific pr... » read more

← Older posts

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?