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RISC-V Targets Data Centers


RISC-V vendors are beginning to aim much higher in the compute hierarchy, targeting data centers and supercomputers rather than just simple embedded applications on the edge. In the past, this would have been nearly impossible for a new instruction set architecture. But a growing focus on heterogeneous chip integration, combined with the reduced benefits of scaling and increasing demand for ... » read more

Slower Metal Bogs Down SoC Performance


Metal interconnect delays are rising, offsetting some of the gains from faster transistors at each successive process node. Older architectures were born in a time when compute time was the limiter. But with interconnects increasingly viewed as the limiter on advanced nodes, there’s an opportunity to rethink how we build systems-on-chips (SoCs). ”Interconnect delay is a fundamental tr... » read more

A Sneak Peek Into SVE And VLA Programming


Download this white paper to get an overview of SVE, get information on the new registers and the new instructions, and learn about the Vector Length Agnostic (VLA) programming technique, including some examples. The Scalable Vector Extension (SVE) is an extension of the ARMv8-A A64 instruction set, recently announced by ARM. Following the announcement at Hot Chips 28, a few articles describ... » read more

The Intelligent Flexible Cloud


Network applications and services today are nearly unrecognizable from a few decades ago. The diversity, scale, and dynamic evolution of apps, services, data, and devices have led to a corresponding evolution within service provider environments. Public, private, and hybrid clouds are ascendant. Software-based approaches to more agile network management and efficiency are being pioneered by ind... » read more