A Novel Tier Partitioning Method in 3DIC Placement Optimizing PPA


A new technical paper titled "PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation" was published by researchers at Seoul National University and Ulsan National Institute of Science and Technology. Abstract "3D ICs are renowned for their potential to enable high-performance and low-power designs by utilizing denser and shorter inter-tier connections. In the physical design f... » read more

ILP-Based Router for Wire-Bonding FBGA Packaging Design


A new technical paper titled "ILP-Based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design" was written by researchers at National Taiwan University of Science and Technology. "In this paper, we propose an integer linear programming (ILP)-based router for wire-bonding FBGA packaging design. Our ILP formulation not only can handle design-depende... » read more