Floorplanning Method For Reducing Thermally-Induced Structural Stress In Chiplet Packages (Penn State, Intel, ASU et al.)


A new technical paper titled "STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration" was published by researchers at Pennsylvania State University, Intel, Arizona State University and University of Notre Dame. Abstract "Chiplet-based architectures and advanced packaging has emerged as transformative approaches in semiconductor design. While conventional ph... » read more

Chip Industry Week in Review


Check out the Inside Chips podcast for our behind-the-scenes analysis. The U.S. government is rescinding a Biden-era AI export rule that would have imposed complex restrictions on how U.S. chip and AI technology is sold abroad, a move welcomed by companies like Nvidia, reports Bloomberg. While new, simpler guidelines are expected in the coming months, the decision introduces short-term uncer... » read more

Chip Industry Week in Review


Check out the Inside Chips podcast for our behind-the-scenes analysis of changes at Intel Foundry. Intel rolled out its updated process technology roadmap this week, along with early process design kit (PDK) for its 14A gate-all-around process technology. That node will utilize high-NA EUV, and include direct contact power delivery, the second generation of its backside power delivery techno... » read more

Chip Industry Week In Review


[Podcast version is here.] TSMC said it will produce 30% of its leading-edge chips in Arizona when all six of its fabs are operational, a total investment of $165 billion, Axios reported. In its latest SEC filing, the foundry said it continues to add capacity in Taiwan, Arizona, Japan, and Germany. The Trump administration launched a Section 232 investigation into semiconductors and relat... » read more

Backside Power Delivery Nears Production


Backside power delivery is being called a game changer — a breakthrough technology and the next great enabler in CMOS scaling. It promises significant PPA advances, including faster switching, lower voltage droop, and reduced power supply noise. And it is poised to deliver these benefits below the 2nm node, despite a substantial disruption in front-end processes from lithography pattern di... » read more

2030 Data Center AI Chip Winners: The Trillion Dollar Club


At the start of 2025, I believed AI was overhyped, ASICs were a niche, and a market pullback was inevitable. My long-term view has changed dramatically. AI technology and adoption is accelerating at an astonishing pace. One of the GenAI/LLM leaders, or Nvidia, will be the first $10 Trillion market cap company by 2030. Large language models (LLMs) are rapidly improving in both capability and ... » read more

Chip Industry Week In Review


Check out our new Inside Chips podcast. President Trump’s ‘Liberation Day’ tariffs were announced this week. The executive order stated that semiconductors and copper imports are not directly subject to the reciprocal tariff, although the exemption may be short-lived. Semiconductor equipment and tools were not mentioned, leaving the industry searching for clarification. Regardless, hig... » read more

Stakes Are High For Aerospace, Defense IC Designs


Chips destined for the skies or armed forces need extra everything. They require higher layers of abstraction to simulate all the moving parts in the field, high-reliability testing for harsh environments, in addition to system-level test. They also need radiation-hardening and ceramic materials for space, extra safety layers, and advanced security techniques. As in the automotive sector, th... » read more

Chip Industry Week In Review


ASML and imec signed a five-year strategic partnership to advance semiconductor innovation and sustainable technology. The collaboration will leverage ASML’s full product portfolio, including high-NA EUV, DUV immersion, and advanced metrology tools, within imec’s pilot line for sub-2nm R&D. Supported by EU and national funding, it will also drive research in silicon photonics, memory, a... » read more

Chip Industry Week In Review


Intel said its new fab in Licking County, Ohio will be delayed due to financial struggles and a need to align chip production with market demand, reported the Columbus Dispatch. Construction is now estimated to be completed in 2030, with operations to start in 2030 or 2031. The company said it already has invested $3.7 billion locally. Apple plans to invest more than $500 billion in the U.S... » read more

← Older posts Newer posts →