Building One Interface Subsystem For Multiple IoT SoCs


When designing SoCs for Internet of Things (IoT) applications, designers quickly realize that their most efficient use of resources will result in chips that can address multiple end applications. Consumer products require connectivity or edge devices, and networking or enterprise companies are broadening their reach to home networking and cloud services, like remote processing, that complement... » read more

Intel Inside The Package


Mark Bohr, senior fellow and director of process architecture and integration at Intel, sat down with Semiconductor Engineering to discuss the growing importance of multi-chip integration in a package, the growing emphasis on heterogeneity, and what to expect at 7nm and 5nm. What follows are excerpts of that interview. SE: There’s a move toward more heterogeneity in designs. Intel clearly ... » read more

IIoT Grows, But So Do Risks


By Jeff Dorsch & Ed Sperling After years of fitful progress, [getkc id="78" kc_name="Industrial Internet of Things"] technology is gaining adoption on the factory floor, in the electrical power grid, and other areas that could do with greater amounts of data analysis and insights from a connected ecosystem. AT&T, General Electric, IBM, Verizon Communications, and other large ... » read more

Secret Sauce To Make Design Reuse A Reality


In a globally competitive landscape, IP reuse and effective team collaboration play a crucial role in product success. But if one considers the complex dynamics of all the recent advances in technology, the insatiable appetite for consumer electronics coupled with the design cost and time-to-market pressures on designers, one would not be unjustified in assuming that the problem of design reuse... » read more

Verification And The IoT


Semiconductor Engineering sat down to discuss what impact the IoT will have on the design cycle, with Christopher Lawless, director of external customer acceleration in [getentity id="22846" e_name="Intel"]'s Software Services Group; David Lacey, design and verification technologist at Hewlett Packard Enterprise; Jim Hogan, managing partner at Vista Ventures; Frank Schirrmeister, senior group d... » read more

Performance-IP: Less Memory Latency


The combination of more functionality on chips plus more contention for memories is forcing companies to look at different ways to improve performance. Just adding more processing power doesn't guarantee improved performance, and throwing more memory at a problem—either SRAM or multiple levels of cache—is expensive and not always faster. There are too many processors and too many request... » read more

Why You Need ASIL Certified Processor IP For Automotive Safety Applications


As the electronics content in automotive safety-related systems continues to grow, there are also an increasing number of new entrants into the automotive semiconductor market. To achieve automotive safety certification, specialized hardware and software is required. With this competitive pressure and consumer demand for safer vehicles, it is more important than ever to focus on cost savings an... » read more

54th DAC Program Finalized


A DAC winter meeting held in sunny Mexico isn’t what it’s cracked up to be. (Although we did enjoy the break from this winter storms!) Everybody thinks the Executive Committee members are lounging on the beach enjoying drinks with little umbrellas in them. That couldn’t be further from the truth! In fact, I and 15 other EC members spent most of our February meetings in Puerto Vallar... » read more

Biz Talk: ASICs


eSilicon CEO [getperson id="11145" comment="Jack Harding"] talks about the future of scaling, advanced packaging, the next big things—automotive, deep learning and virtual reality—and the need for security. [youtube vid=leO8gABABqk]   Related Stories Executive Insight: Jack Harding (Aug 2016) eSilicon’s CEO looks at industry consolidation, competition, China’s impact, an... » read more

Challenges Grow For IP Reuse


As chip complexity increases, so does the complexity of IP blocks being developed for those designs. That is making it much more difficult to re-use IP from one design to the next, or even to integrate new IP into an SoC. What is changing is the perception that standard [getkc id="43" kc_name="IP"] works the same in every design. Moreover, well-developed [getkc id="100" kc_name="methodologie... » read more

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