Chiplets Enter The Supercomputer Race

By Mark LaPedus - 17 Mar, 2022 - Comments: 0

Several entities from various nations are racing each other to deliver and deploy chiplet-based exascale supercomputers, a new class of systems that are 1,000x faster than today’s supercomputers. The latest exascale supercomputer CPU and GPU designs mix and match complex dies in advanced packages, adding a new level of flexibility and customization for supercomputers. For years, various na... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 25 Feb, 2022 - Comments: 0

Chipmakers, OEMs UMC plans to build a new fab next to its existing 300mm fab in Singapore. The new fab, called Fab12i P3, will manufacture wafers based on UMC’s 22nm/28nm processes. The planned investment for this project will be $5 billion. The first phase of this greenfield fab will have a monthly capacity of 30,000 wafers with production expected to commence in late 2024. To account fo... » read more

New Power, Performance Options At The Edge

By Heidi Elliott - 21 Jul, 2021 - Comments: 0

Increasing compute intelligence at the edge is forcing chip architects to rethink how computing gets partitioned and prioritized, and what kinds of processing elements and memory configurations work best for a particular application. Sending raw data to the cloud for processing is both time- and resource-intensive, and it's often unnecessary because most of the data collected by a growing nu... » read more

System Bits: March 19

By Jeff Dorsch - 19 Mar, 2019 - Comments: 0

Nanomesh material could find use in sustainable applications Imec collaborated with KU Leuven to develop a nanomesh material made of a 3D structure with nanowires. This material could prove to make batteries more energy-efficient, while also improving catalytic converters and fuel cells, and making hydrogen production easier. The research team is touting the 3D nanometer-scale metal grid st... » read more

System Bits: March 11

By Jeff Dorsch - 11 Mar, 2019 - Comments: 0

Cryptography IC for the IoT Massachusetts Institute of Technology researchers report their development of a cryptographic circuit that could be used to protect low-power Internet of Things devices when quantum computing takes hold. [caption id="attachment_24144905" align="alignleft" width="300"] Image Credit: MIT[/caption] The research team presented a paper at the 2019 International Sol... » read more

A Conference For The Ages

By Mike Gianfagna - 28 Feb, 2019 - Comments: 0

The International Solid-State Circuits Conference (ISSCC) was held recently in its permanent location at the San Francisco Marriott Marquis. eSilicon had the honor of both presenting our SerDes capabilities and demonstrating the technology as well. More about that later. First, I’d like to examine the institution called ISSCC. The first ISSCC was held in 1954 in Philadelphia. Yes, 1954, that�... » read more

System Bits: Feb. 26

By Jeff Dorsch - 26 Feb, 2019 - Comments: 0

Firefly microstructures in LED light bulbs Pennsylvania State University researchers wanted to improve the energy efficiency of commercial light-emitting diode light bulbs to save even more energy. They found the answer in the lantern surface of fireflies. "LED lightbulbs play a key role in clean energy," said Stuart (Shizhuo) Yin, professor of electrical engineering at Penn State. "Overall... » read more

5 Top Storylines For NAND Biz

By Mark LaPedus - 21 Feb, 2019 - Comments: 0

2019 is expected to be a busy, if not difficult, year in the NAND flash memory market. Vendors will continue to ramp up 3D NAND, the successor to traditional 2D or planar NAND. Then, over the last year, prices for NAND have dropped with oversupply in the market. What’s in store in 2019? Vendors are expected to rush out their next-generation products. Then, there is a debate whether the... » read more

Rush Hour On The Technology Roadmap

By Mike Gianfagna - 30 Jan, 2017 - Comments: 0

Starting this week, the International Solid State Circuits Conference (ISSCC) will commence at the Marriott in downtown San Francisco. This prestigious conference showcases the latest semiconductor innovations from around the world. Looking at the advance program, one can’t help but notice a shift in the work presented. The conference theme this year is: “Intelligent Chips for a Smart World... » read more

28, 20nm Nodes Demand Advanced Power Management

By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler With the complexity of getting 28 and 20nm designs to reach desired yields with the desired power and performance on the shoulders of design teams, advanced power management techniques are a must. Sub-clock power gating, clock power gate structures, adaptive body bias and other techniques are making it possible. Sub-Clock Power Gating Far from a new techniqu... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?