What Will That Chip Cost?

By Brian Bailey - 30 Oct, 2023 - Comments: 1

In the past, analysts, consultants, and many other experts attempted to estimate the cost of a new chip implemented in the latest process technology. They concluded that by the 3nm node, only a few companies would be able to afford them — and by the time they got into the angstrom range, probably nobody would. Much has changed over the past few process nodes. Increasing numbers of startups... » read more

Steering The Semiconductor Industry

By Brian Bailey - 26 Aug, 2021 - Comments: 2

Progress in semiconductors has been one of the most successful engineering feats, and the industry has ridden an exponential curve longer than anything else in history. It is also a highly conservative industry that has pushed away many disruptive changes in favor of small incremental changes that minimize risk. There have been significant changes over the decades, and they often required a ... » read more

First Look: 5nm

By Ann Mutschler - 15 Oct, 2015 - Comments: 3

By the time the 5nm semiconductor manufacturing process node reaches mass production readiness, the hurdles and challenges will no longer be open for discussion. But as of this moment, some of them seem almost insurmountable, raising new questions about the continued viability of Moore's Law. There has been much written about the end of [getkc id="74" comment="Moore's Law"] for nearly two de... » read more

Raise A Fence, Dig A Tunnel, Build A Bridge

By Ed Sperling - 17 Sep, 2015 - Comments: 0

There are three main options for chipmakers over the course of the next decade. Which option they choose depends upon their individual needs, talents, and how much and what kind of differentiation they believe will matter to them. The options roughly fall into three categories—fence, bridge or tunnel. The fence option Rather than changing anything, the entire ecosystem can stick to wha... » read more

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Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: ITRS roadmap

What Will That Chip Cost?

Steering The Semiconductor Industry

First Look: 5nm

Raise A Fence, Dig A Tunnel, Build A Bridge

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Entities, people and technologies explored