How To Solve Frequency Jitter In Constant On-Time POLs With A Ripple Injection Circuit

By Tammie Bard - 01 Aug, 2024 - Comments: 0

The purpose of this article is to walk through the steps of implementing a ripple injection circuit for constant on-time POLs. It covers how to connect the circuit and then how to calculate the values used in the circuit. Frequency jitter can be caused by a number of things such as noise injection into the voltage sense lines from outside sources, to very low ripple current in the output ind... » read more

Testing PCI Express 5.0 PHY Transmitter Performance Without Analysis Software

By Synopsys - 12 Jun, 2024 - Comments: 0

PCI Express (PCIe) 5.0 silicon characterization across process, voltage, and temperature variations, is necessary for accelerating SoC designs. To measure key qualifying parameters, designers and test engineers must have a good understanding of the PCIe 5.0 base electrical specification and know the physical layer’s design architecture and features for accurate characterization of 32GT/s PHY ... » read more

Power Supply Noise Effects On Jitter In Clock Synchronous Systems With Emphasis On Memory Interfaces

By Synopsys - 23 Aug, 2023 - Comments: 0

In today's fast-paced digital world, the performance and capacity of high-speed memory has become crucial for a wide range of applications, from personal computing devices to data centers and high-performance computing systems. Designers face challenges in optimizing their designs for speed, power efficiency, and reliability — all while ensuring robustness in the face of power supply noise. T... » read more

Power Supply Noise Effects On Jitter In Clock Synchronous Systems With Emphasis On Memory Interfaces

By Synopsys - 09 Aug, 2023 - Comments: 0

Power Supply Noise Effects on Jitter in Clock Synchronous Systems with Emphasis on LPDDR5X, DDR5 and HBM3 In today's fast-paced digital world, the performance and capacity of high-speed memory has become crucial for a wide range of applications, from personal computing devices to data centers and high-performance computing systems. Designers face challenges in optimizing their designs ... » read more

Jitter Budgeting For Clock Distribution Networks In High-Speed PHYs And SerDes

By Synopsys - 07 Dec, 2022 - Comments: 0

This paper presents a simple but practically precise estimation of periodic single-tone power supply induced jitter (PSIJ) for MOS clock buffer chains. The estimation is algebraically simple for its analytical closed-form expression requiring only a few circuit simulation results without the pre-knowledge of circuit device SPICE parameters. The expression is well suited to predict period PSIJ, ... » read more

Dynamic CDC Jitter For Clock Domain Crossing (CDC) Signoff

By Himanshu Bhatt - 16 Jan, 2020 - Comments: 0

By Himanshu Bhatt and Paras Mal Jain Detecting and debugging deep sequential CDC convergences using structural CDC verification is extremely difficult since doing a flat analysis on large designs has capacity related challenges, and even if verification tools can complete the analysis, it becomes a nightmare to debug the violations with complex sequential logic. Thus arises the need for dyna... » read more

Wrestling With High-Speed SerDes

By Ann Mutschler - 19 Jun, 2019 - Comments: 2

SerDes has emerged as the primary solution in chips where there is a need for fast data movement and limited I/O, but this technology is becoming significantly more challenging to work with as speeds continue to rise to offset the massive increase in data. A Serializer/Deserializer is used to convert parallel data into serial data, allowing designers to speed up data communication without h... » read more

Engineering The Signal For GDDR6

By Shawn Nikoukary - 09 May, 2019 - Comments: 0

DDR1 through DDR3 had their challenges, but speeds were below one gigabit and signal integrity (SI) challenges were more centered around static timing and running pseudo random binary sequence (PRBS) simulations. Now, with GDDR6, we are working on 16 to 20 gigabits per second (Gbps) signaling and even faster in the near future. As a result, engineering the signal for GDDR6 will require careful ... » read more

Symptoms Of SoC Electromagnetic (EM) Crosstalk

By Anand Raman - 14 Feb, 2018 - Comments: 0

By Anand Raman and Magdy Abadir Have you ever had your silicon demonstrate unexpected behavior? Have you ever found unexplainable design failure or performance degradation? A number of issues could be the culprit - from overloaded signal nets, a noisy power grid, or increasing temperature - but one problem often overlooked is electromagnetic (EM) crosstalk. Electromagnetic (EM) crosstal... » read more

Noise Abatement

By Brian Bailey - 12 Oct, 2017 - Comments: 0

[getkc id="285" kc_name="Noise"] is a fact of life. Almost everything we do creates noise as a by-product and quite often what is a signal to one party is noise to another. Noise cannot be eliminated. It must be managed. But is noise becoming a larger issue in chips as the technology nodes get smaller and packaging becomes more complex? For some, the answer is a very strong yes, while for ot... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: jitter

How To Solve Frequency Jitter In Constant On-Time POLs With A Ripple Injection Circuit

Testing PCI Express 5.0 PHY Transmitter Performance Without Analysis Software

Power Supply Noise Effects On Jitter In Clock Synchronous Systems With Emphasis On Memory Interfaces

Power Supply Noise Effects On Jitter In Clock Synchronous Systems With Emphasis On Memory Interfaces

Jitter Budgeting For Clock Distribution Networks In High-Speed PHYs And SerDes

Dynamic CDC Jitter For Clock Domain Crossing (CDC) Signoff

Wrestling With High-Speed SerDes

Engineering The Signal For GDDR6

Symptoms Of SoC Electromagnetic (EM) Crosstalk

Noise Abatement