Hypervisors: Help Or Hindrance?

By Brian Bailey - 29 Sep, 2016 - Comments: 0

Hypervisors are seeing an increased level of adoption, but do they help or hinder the development and verification process? The answer may depend on your perspective. In the hardware world, system-level integration is rapidly becoming a roadblock in the development process. While each of the pieces may be known to work separately, as soon as they are put together, the interactions between th... » read more

The Rise Of Complex Debug On Heterogeneous Multicore SoCs

By Kathy Tufto - 25 Aug, 2016 - Comments: 0

When projects move away from discrete development of loosely coupled systems to an integrated heterogeneous environment, elephantine debugging challenges are created. These challenges do not exist during discrete development because developers are able to design, develop, test, and optimize within the confines of their own device. But when consolidating heterogeneous systems, developers and ... » read more

Optimizing Emulator Utilization

By Russell Klein - 11 Aug, 2016 - Comments: 0

The growing pressures of market schedules, design complexity and the ever-increasing amount of embedded software in today’s SoCs has put verification in the hot-seat. Now that new emulation tools can link hardware and software verification, SoC designers are turning to emulation more than ever before to debug embedded software. The standard method for debugging software with an emulator is wi... » read more

The JTAG Connection

By Ernest Worthman - 02 Oct, 2014 - Comments: 0

It is fairly common knowledge that hacking into today’s intelligent Internet devices is child’s play in most cases. The main reason is that the devices have little or no innate security designed in. When they do have some level of security, it is generally provisioned by software running on the host system, to which the devices are connected. But that only works with a device on the grid. O... » read more

Software Debug Gets Tricky

By Ann Mutschler - 11 Jul, 2013 - Comments: 0

By Ann Steffora Mutschler As designs continue to grow in size and complexity, that complexity has led to an increasing number of processing cores. Additional cores, in turn, allow for additional software to be run on those cores, and debugging the software becomes critical. Traditionally, emulation has played a significant role in verifying that software against RTL code, and continues to d... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: JTAG

Hypervisors: Help Or Hindrance?

The Rise Of Complex Debug On Heterogeneous Multicore SoCs

Optimizing Emulator Utilization

The JTAG Connection

Software Debug Gets Tricky