The Week In Review: Design

Adesto buys S3 Semi; high-reliability analog; Intel bets on IP generation and RISC-V.

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M&A
IoT-focused memory chipmaker Adesto Technologies acquired S3 Semiconductors, a provider of mixed-signal and RF ASICs and IP. Based in Ireland, S3 Semiconductors was founded in 1986. S3 Semiconductors will become a business unit of Adesto and will continue to operate under its current model in the $35 million deal. S3 Semiconductor’s parent company, S3 Group, will continue as a separate company focused on smart medical devices.

Tools
Cadence debuted a new design-for-reliability tool for analog and mixed-signal IC design. The Legato Reliability Solution incorporates analog defect analysis and simulation to evaluate the ability to eliminate die with manufacturing defects and resulting test escapes that cause field failures, as well as electro-thermal and aging analysis to prevent thermal overstress and predict wear-out.

Aldec made several updates to its Riviera-PRO verification platform, adding a UVM Register Generator for automated register model creation. The UVM Register Generator supports input of IP-XACT component files and CSV files. Other additions include a Unit Linting function that runs ALINT-PRO in the background and support for the latest extensions to VHDL.

XJTAG uncorked free DFT software for users of Mentor’s Xpedition product to increase the design for test and debug capabilities of the schematic capture and PCB design environment. XJTAG DFT Assistant helps validate correct JTAG chain connectivity by finding and repairing errors.

IP
Arasan Chip Systems uncorked its MIPI I3C Host Controller Interface (I3C HCI) Master IP core compliant to the recently released MIPI I3C HCI Specification 1.0. The IP kit includes a Linux software stack compatible with the I3C HCI Master IP Core, an I3C Hardware Development Kit to enable prototyping and compliance testing of I3C products, and the I3C Slave IP Core.

Chips&Media launched its first computer vision IP, which implements a convolutional neural network capable of processing 4K resolution at 60 frames per second input in real-time for object detection. The IP targets edge devices for automotive and surveillance applications.

Chipus taped out a set of its ultra-low power analog IP on SilTerra’s 0.18um I18L IoT Platform. The test chip includes a temperature sensor, RTC oscillators, 6MHz oscillators, and an ultra-low power bandgap reference.

Standards
The Si2 Compact Model Coalition published the Open Model Interface, a C-language application programming interface that supports SPICE compact model extensions. OMI allows for simulation and analysis of physical effects such as self-heating and aging as well as design optimization. It is based on TMI2, the TSMC Model Interface, which was donated to Si2 by TSMC in 2014. So far, OMI supports BSIM, BSIM-CMG, HiSIM2, and BSIM-SOI.

The MIPI Alliance released MIPI Touch, a family of publicly available specifications for the design and implementation of touch applications, such as in smartphones. The effort ties together several MIPI specifications for touch, sensor, and software integration: MIPI Touch Command Set (MIPI TCS) for writing device drivers across operating systems; MIPI Touch Adaptation Layer for I3C (MIPI ALI3C) to translate touch commands for use on the MIPI I3C protocol; MIPI I3C Host Controller Interface (MIPI I3C HCI), which enables touch commands and multiple data streams for advanced systems; and MIPI I3C v1.0, which connects an application processor to a touch sensor.

Deals
Rambus and GigaDevice formed a joint venture, Reliance Memory, in China to focus on development and commercialization of Resistive Ram (RRAM), a non-volatile memory that works by changing the resistance of materials when different voltages are applied. The joint venture has investment funding from THG Ventures, West Summit Capital, Walden International, and Zhisland Capital.

Esperanto Technologies inked deals for both NetSpeed Systems’ network-on-chip IP and design environment and UltraSoC’s embedded analytics and debug IP for its Supercomputer-on-a-Chip for AI applications. The 7nm chip will integrate thousands of RISC-V compatible processors each with vector/tensor accelerators.

NetSpeed Systems and Northwest Logic are teaming up on a high throughput memory subsystem solution that uses NetSpeed’s interconnect IP and Northwest Logic’s HBM2 and GDDR6 memory controllers for customers designing SoCs for hyperscale and automotive applications. The companies will provide a common platform to extend NetSpeed’s dynamic-priority elevation approach to the memory controller so that system-level traffic-flow priorities are handled in an end-to-end solution.

Numbers
Intel Capital placed investments in two firms: Movellus and SiFive. Movellus provides generator tools enabling automatic creation and implementation of PLL, DLL, and LDO digital IP and will use the funds to accelerate market deployment and adoption of its technology. SiFive is a provider of RISC-V IP cores, SoCs, and development boards, as well a RISC-V-focused IP catalog.

Rambus released financial results for first quarter 2018 with revenue of $46.4 million. On a GAAP basis, there was a loss per share of $0.36; on a non-GAAP basis there was a loss per share of $0.10. Rambus changed to a new reporting standard this year; under the previous reporting standard, revenue for Q1 2018 was $100.5 million, up 4% from the same quarter last year. GAAP income per share for the quarter was $0.05, up 66.7% from $0.03 in Q1 2017; non-GAAP income per share was $0.21, up 23.5% from $0.17. The company posted record revenue for its memory and interface IP cores.



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