tag: Si2

Chip Industry Week in Review
By The SE Staff - 10 Oct, 2025 - Comments: 0

SEMICON West was held in Phoenix this week, with presentations covering heterogeneous integration, AI, quantum, supply chain resilience, and more. Amid the buzz of the conference, some key manufacturing and test announcements were made this week: The strategic importance of the Phoenix area hub was highlighted. Amkor Technology broke ground this week on its advanced packaging and test camp... » read more

Chip Industry Week in Review
By The SE Staff - 08 Aug, 2025 - Comments: 1

Apple plans to increase its U.S. investment by an additional $100 billion over four years, which includes the launch of an advanced manufacturing supply chain program, spurring a number of related chip industry announcements, including: Apple will invest in Amkor's new packaging and test facility in Arizona as its first and largest customer, and Amkor will package and test Apple silicon pr... » read more

Chip Industry Week in Review
By The SE Staff - 03 Jul, 2025 - Comments: 0

[Editor's Note: Early edition due to the U.S. July 4th holiday.] The U.S. government lifted export restrictions that barred Synopsys, Siemens EDA, and Cadence from selling EDA tools to China. In a statement, Synopsys said it received a letter from the U.S. Commerce Department immediately rescinding those restrictions. Siemens issued a similar statement. Which tools or hardware accelerated t... » read more

Chip Industry Week In Review
By The SE Staff - 28 Mar, 2025 - Comments: 0

McKinsey issued a new report on the state of the chemical supply chain for semiconductors in the U.S., citing potential shortages of high-purity materials such as tungsten, aluminum and copper, lack of access to CMP slurries and photoresists for EUV, and rising competition for high-k precursors that can fetch higher prices outside of the U.S. CSIS weighed in on the U.S. goverment's recent ... » read more

Chip Industry Week In Review
By The SE Staff - 14 Mar, 2025 - Comments: 0

ASML and imec signed a five-year strategic partnership to advance semiconductor innovation and sustainable technology. The collaboration will leverage ASML’s full product portfolio, including high-NA EUV, DUV immersion, and advanced metrology tools, within imec’s pilot line for sub-2nm R&D. Supported by EU and national funding, it will also drive research in silicon photonics, memory, a... » read more

Reusable Power Models
By Brian Bailey - 14 Aug, 2024 - Comments: 0

Power is not a new concern, and proprietary models are available for some tasks, but the industry lacks standardization. The Silicon Integration Initiative (Si2) is hoping to help resolve that with an upcoming release of IEEE 2416, based on its Unified Power Model (UPM) work. The creation of any model is not to be taken lightly. There is a cost to its creation, verification and maintenance. ... » read more

Uneven Circuit Aging Becoming A Bigger Problem
By Ann Mutschler - 09 Mar, 2023 - Comments: 0

Circuit aging is emerging as a first-order design challenge as engineering teams look for new ways to improve reliability and ensure the functionality of chips throughout their expected lifetimes. The need for reliability is obvious in data centers and automobiles, where a chip failure could result in downtime or injury. It also is increasingly important in mobile and consumer electronics, w... » read more

Week In Review: Design, Low Power
By Jesse Allen - 10 Feb, 2023 - Comments: 0

Arm is heading for an IPO this year, with plans "fairly well developed and underway now," CEO Rene Haas told Reuters. Arm reported fiscal Q3 revenue of $746 million, up 28% compared with the same period in 2021, setting the stage for a public offering. The company noted it had double- or triple-revenue increases in automotive, consumer, infrastructure, and IoT. The Si2 Compact Model Coalit... » read more

Power Issues Causing More Respins At 7nm And Below
By Brian Bailey - 26 Jan, 2023 - Comments: 0

Power consumption has been a major design consideration for some time, but it is far from being a solved issue. In fact, an increasing number of designs have a plethora of power-related problems, and those problems are getting worse in new chip designs. Many designs today are power-limited — or perhaps more accurately stated, thermal-limited. A chip only can consume as much power as it is ... » read more

Designing For Multiple Die
By Ann Mutschler - 21 Dec, 2022 - Comments: 1

Integrating multiple die or chiplets into a package is proving to be very different than putting them on the same die, where everything is developed at the same node using the same foundry process. As designs become more heterogeneous and disaggregated, they need to be modeled, properly floor-planned, verified, and debugged in the context of a system, rather than as individual components. Typi... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy