Design For Advanced Packaging


Advanced packaging techniques are viewed as either a replacement for Moore's Law scaling, or a way of augmenting it. But there is a big gap between the extensive work done to prove these devices can be manufactured with sufficient yield and the amount of attention being paid to the demands advanced packaging has on the design and verification flows. Not all advanced packaging places the same... » read more

Week In Review: Manufacturing, Test


Chipmakers Amid ongoing delays with its 10nm process, Intel has reorganized its manufacturing unit, according to a report from The Oregonian/OregonLive. Sohail Ahmed, who has jointly led the unit since 2016, will retire next month, according to the report. The industry is racing to put extreme ultraviolet (EUV) lithography into production. TSMC recently taped-out its first 7nm chip using E... » read more

Week In Review: Design, Low Power


Arm announced its new roadmap promising 30% annual system performance gains on leading edge nodes through 2021. These gains are to come from a combination of microarchitecture design to hardware, software and tools. They are branding this new roadmap 'Neoverse.' The first delivery will be Ares – expected in early 2019 – for a 7nm IP platform targeting 5G networks and next-generation cloud t... » read more

Week In Review: Design, Low Power


Deals AI startup Enflame (Suiyuan) Technology purchased multiple licenses of Arteris IP's FlexNoC interconnect IP for use as the on-chip communications backbone of its AI training chips for use in cloud datacenters. Enflame cited easy creation of regular topologies used in AI chips and the ability to take advantage of HBM2 memories. Phison, a maker of NAND flash controller ICs, inked... » read more

Aging In Advanced Nodes


Semiconductor Engineering sat down to discuss design reliability and circuit aging with João Geada, chief technologist for the semiconductor business unit at ANSYS; Hany Elhak, product management director, simulation and characterization in the custom IC and PCB group at Cadence; Christoph Sohrmann, advanced physical verification at Fraunhofer EAS; Magdy Abadir, vice president of marketing at ... » read more

Week In Review: Design, Low Power


Aldec expanded the rule-checking capabilities of its ALINT-PRO tool, adding twice as many FSM checks and new graphical representations to aid state exploration. Also included is enhanced setup automation for complex Xilinx Vivado and ISE projects that automatically organizes a workspace to deliver hierarchical and incremental DRC and CDC analysis. Xilinx acquired AI startup DeePhi Technology... » read more

The Week In Review: Design


M&A IoT-focused memory chipmaker Adesto Technologies acquired S3 Semiconductors, a provider of mixed-signal and RF ASICs and IP. Based in Ireland, S3 Semiconductors was founded in 1986. S3 Semiconductors will become a business unit of Adesto and will continue to operate under its current model in the $35 million deal. S3 Semiconductor's parent company, S3 Group, will continue as a separate... » read more

The Week In Review: Design


M&A The ESD Alliance is merging with SEMI, becoming a SEMI Strategic Association Partner. SE Editor In Chief Ed Sperling argues that the merger has broad implications for the chip industry, particularly as smaller nodes require greater collaboration between design and manufacturing. Meanwhile, SEMI president and CEO Ajit Manocha explains why the combining will be of benefit to members of b... » read more

Blog Review: Apr. 18


Cadence's Meera Collier provides an overview of five emerging technologies that could drive the semiconductor industry in the future, from carbon nanotubes to quantum computing. Mentor's Colin Walls reminds embedded software developers of a few common sense tips, including better readability with braces in C/C++ and monitoring stack overflow. Synopsys' Tim Mackey rounds up the last few we... » read more

What Happened To UPF?


Two years ago there was a lot of excitement, both within the industry and the standards communities, about rapid advancements that were being made around low-power design, languages and methodologies. Since then, everything has gone quiet. What happened? At the time, it was reported that the [gettech id="31043" comment="IEEE 1801"] committee was the largest active committee within the IEEE. ... » read more

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