Week In Review: Design, Low Power

By Jesse Allen - 15 Jan, 2021 - Comments: 0

Qualcomm will acquire data center chip startup Nuvia for approximately $1.4 billion. Nuvia is working on a data center SoC and Arm-based CPU core it claims will lower performance per total cost of ownership by matching high performance with high efficiency and limiting maximum power to that which can be dissipated in an air-cooled environment. Qualcomm said Nuvia's technology would be incorpora... » read more

Week In Review: Design, Low Power

By Jesse Allen - 24 Apr, 2020 - Comments: 0

Tools & IP Codasip unveiled its Codasip SweRV Core EH1 Support Package, which provides support for Western Digital's open source RISC-V-based core. The support package provides a comprehensive set of tools and components needed to design, implement, test, and write software for a SweRV Core-based SoC with support for leading EDA open and commercial flows. A free basic version is available ... » read more

Chips&Media: Design and Verification of Deep Learning Object Detection IP

By Mentor, a Siemens Business - 30 Jan, 2019 - Comments: 0

Chips&Media, a leading provider of high-performance video IP for SoC design, took a unique approach to designing their latest IP for detecting objects in real time. They decided to adopt a new High-Level Synthesis (HLS) flow to implement their deep learning algorithm. But, they would have an RTL team create this algorithm, using traditional tools and another team would employ the Catapult H... » read more

Week in Review: IoT, Security, Auto

By Jeff Dorsch - 18 Jan, 2019 - Comments: 0

Internet of Things A dairy barn without any people working in it. An automated greenhouse for produce. Coming soon, little robots that will weed crop fields and look for diseased plants. This is Rivendale Farms, in the countryside west of Pittsburgh, which is 175 acres serving as a beta site for agricultural Internet of Things technology. The small farm has about 150 Jersey cows, each of which... » read more

Week In Review: Design, Low Power

By Jesse Allen - 18 Jan, 2019 - Comments: 0

M&A Rambus acquired the assets of Diablo Technologies. Founded in 2003, Diablo Technologies specialized in NVDIMM technologies, but was hit with a patent lawsuit by Netlist in 2013. While Diablo won the lawsuit and several subsequent appeals, it declared bankruptcy in December 2017. Rambus says the technology will provide a foundation for integrating existing DRAM and Flash along with emer... » read more

The Week In Review: Design

By Jesse Allen - 11 May, 2018 - Comments: 0

M&A IoT-focused memory chipmaker Adesto Technologies acquired S3 Semiconductors, a provider of mixed-signal and RF ASICs and IP. Based in Ireland, S3 Semiconductors was founded in 1986. S3 Semiconductors will become a business unit of Adesto and will continue to operate under its current model in the $35 million deal. S3 Semiconductor's parent company, S3 Group, will continue as a separate... » read more

The Week In Review: Design

By Jesse Allen - 02 Jun, 2017 - Comments: 0

Tools OneSpin revealed new formal applications focused on random fault verification for safety critical analysis in automotive and other mission-critical applications. The Fault Injection App provides controlled injection of faults and assertion mapping to associated fault scenarios, as well as visibility into corrupted design behavior. The Fault Detection App allows the detection of dangerous... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: Chips&Media

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Chips&Media: Design and Verification of Deep Learning Object Detection IP

Week in Review: IoT, Security, Auto

Week In Review: Design, Low Power

The Week In Review: Design

The Week In Review: Design