Week In Review: Design, Low Power

Rambus buys Diablo memory assets; partitioning FPGA prototypes; application security.


Rambus acquired the assets of Diablo Technologies. Founded in 2003, Diablo Technologies specialized in NVDIMM technologies, but was hit with a patent lawsuit by Netlist in 2013. While Diablo won the lawsuit and several subsequent appeals, it declared bankruptcy in December 2017. Rambus says the technology will provide a foundation for integrating existing DRAM and Flash along with emerging memories into advanced hybrid memory systems.

The value of semiconductor mergers and acquisitions continued to fall in 2018, according to market research firm IC Insights. M&A activity was valued at $23.2 billion in 2018 compared to $28.1 billion in 2017, down significantly from 2015’s record high of $107.3 billion. However, recent years still outstrip the 2010-2014 period, which averaged $12.6 billion in acquisitions each year.

Aldec debuted the latest version of its ASIC/SoC verification environment, HES-DVM. It adds design partitioning and partition interconnection tools to aid FPGA prototyping, with the ability to evaluate various partitioning scenarios for the best performance on a given prototyping board. Automatic Routing, one addition, automatically resolves feed-through connections if there are no appropriate chip-to-chip traces on a prototyping board; Automatic Physical Connections for multi-FPGA prototyping boards routes all inter-partition connections using available chip-to-chip traces and assigns various types of I/O.

Synopsys updated its Coverity static application security testing software. New features enable analysis of source code without a full build operation, expanded language and framework coverage (including TypeScript, .NET Core, Swift 4.1, and Ruby on Rails), and more accurate detection of client-side and back-end web services vulnerabilities.

Baidu licensed Arteris IP’s FlexNoC interconnect IP for use in its high-performance Kunlun AI cloud chip for data center. Baidu cited the ability to enable high bandwidth on-chip communications as well as load-balanced data traffic to off-chip memory and simplified backend timing closure.

Chips&Media deployed Mentor’s Catapult HLS Platform to design and verify its c.WAVE computer vision IP for real-time object detection. Chips&Media said HLS cut project time in half compared to an RTL flow on the same project, and plan to use it in future products.

Habana Labs used Synopsys’ DesignWare Controller and PHY IP for PCIe 4.0 in its Goya inference processor SoC, which recently saw first-pass silicon success. The company cited the IP’s track record and features supporting data-intensive SoCs. Habana Labs is also integrating the PCIe IP into its next-generation Gaudi training processor SoC.

DVCon 2019: Feb. 25-28 in San Jose, CA. This year’s keynote will argue why it’s important to have an integrated digitalization strategy. Other highlights include a tutorial covering new features in IEEE 1800.2-UVM, a workshop on functional coverage in SystemC, and panels on deep learning and the verification of open ISAs. Advanced registration rates close Jan. 28.

DATE 2019: Mar. 25-29 in Florence, Italy. The conference and exhibition will feature keynotes on heterogeneous computing in cloud and HPC as well as the limitations of modeling frameworks for intelligent systems. Sessions will highlight emerging design technologies, design and test of secure systems, embedded systems for deep learning, and more. Advanced registration closes Mar. 13.

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