The Week In Review: Design

ARM’s new cores target edge AI; random fault verification with formal; virtual emulation; eFPGAs.


OneSpin revealed new formal applications focused on random fault verification for safety critical analysis in automotive and other mission-critical applications. The Fault Injection App provides controlled injection of faults and assertion mapping to associated fault scenarios, as well as visibility into corrupted design behavior. The Fault Detection App allows the detection of dangerous random faults or faults not detected by the safety mechanism. Additionally, the Fault Propagation App was updated to include a new debugger and support for SystemVerilog Assertions (SVA) and Property Specification Language (PSL).

Cadence launched VirtualBridge Adapter, a virtual emulation technology allowing user applications and OS drivers to establish a virtual protocol connection to Palladium platforms. The adapter consists of a transactor that enables high-speed transactions between a user’s design under test and a host workstation, allowing a user’s application to drive traffic via their existing OS driver into the transactor, either directly on the same host workstation or via a networked connection. The software is aimed at accelerating software bring-up in pre-silicon verification versus RTL simulation.

Cadence also released an automated co-design and verification flow between the Virtuoso platform and Allegro and Sigrity technologies to provide a single platform for IC-and package/system-level design capture, analysis, and verification. According to the company, the platform can reduce layout versus schematic (LVS) time between IC and package from days to minutes. The platform is targeted for designs that integrate multiple heterogeneous ICs, including RF, analog, and digital devices.

ARM unveiled the Cortex-A75 and Cortex-A55 processors, the first based on the company’s DynamIQ heterogeneous multicore technology.

The Cortex-A75 is focused on performance and boosts single-thread performance using a fully out-of-order, variable-length, and symmetrical three-way superscalar pipeline, improving performance 20% over the Cortex-A73 when compared at same frequencies, according to ARM. The Cortex-A75 can be used standalone with up to 4 high-performance processors, or in big.LITTLE combination with the Cortex-A55 processor, with up to 8 processors total.

The midrange Cortex-A55 focuses on efficiency, providing up to 2x more memory performance and 15% better power efficiency than Cortex-A53 at iso-frequency, iso-process while offering 10x more scalability with over 3000 unique configurations. Both cores feature private L2 caches and a unified shared L3 cache that can be used across all processors in the DynamIQ cluster.

The Mali-G72 graphics processor, based on the Bifrost architecture, has an expected 1.4x overall graphics performance of the G71, with 25% higher energy efficiency and 20% better area efficiency, says ARM. Tile buffer memory has been increased, and rarely-used instructions were replaced with sequences of simpler instructions.

The IPs add dedicated AI instructions, placing a bet on the growth of machine learning at the edge. In particular, new architectural instructions were added to the Cortex-A55 NEON pipeline, allowing it to perform sixteen 8-bit integer operations per-cycle or eight 16-bit float operations per-cycle, and rounding double MAC instructions. The Mali-G72 boasts a 17% increase in machine learning efficiency over the G71.

Flex Logix completed design of its second-generation high-performance eFPGA IP core for TSMC 16FF+ and 16FFC processes. The EFLX-2.5K can be arrayed to build any size embedded array required, from 1×1 (2.5K LUTs) up to 7×7 (122.5K LUTs). Flex Logix offers logic and DSP versions, and the cores are targeted at networking, base station, data center accelerator and deep learning chips.

Synopsys added the VESA Display Stream Compression (DSC) encoder to its MIPI DSI Host Controller IP. The IP supports ultra-high-resolution quad HD or 4K displays with refresh rates at 60Hz or higher for both image and video. The company says the integrated IP reduces memory size and data transmission bandwidth to lower power consumption and area.

Chips&Media rolled out new Image Signal Processing (ISP) IPs developed to specifically support 2MP, 5MP and 8MP sensors and specialized for requirements of surveillance and automotive products, such as low light environment optimization.

Konica Minolta adopted Synopsys’ ZeBu Server emulation system as its standard hardware platform for verification and early software bring-up on their multi-function printer (MFP) SoC designs, citing the system’s multi-MHz runtime performance.

Leave a Reply

(Note: This name will be displayed publicly)