Oscilloscopes: The EE’s Stethoscope

By Gale Morrison - 17 Nov, 2016 - Comments: 0

Oscilloscopes are like the electricity to your house. You don't give it much thought until a storm knocks it out. The entire electronics industry can't function without oscilloscopes. But this equipment is such a constant and so consistent, we sometimes forget it's there. Semiconductor Engineering spent time with three Test & Measurement (T&M) industry stalwarts to talk about Oscillo... » read more

No More Easy IP Money

By Brian Bailey - 14 Jul, 2016 - Comments: 2

The semiconductor intellectual property ([getkc id="43" kc_name="IP"]) industry is two decades old, but questions are still being asked about what's wrong with it and what needs to be fixed. Normally these kinds of issues are reserved for fast-moving, young industries, not one that is the backbone of semiconductors. Design reuse has become an indispensable part of the design of nearly all el... » read more

Waiting For 5G Technology

By Mark LaPedus - 23 Jun, 2016 - Comments: 1

For some time, carriers, equipment OEMs and chipmakers have been gearing up for the next-generation wireless standard called 5th generation mobile networks, or 5G. 5G is the follow-on to the current wireless standard known as 4G, or long-term evolution (LTE). It will enable data transmission rates of more than 10Gbps, or 100 times the throughput of LTE. But the big question is whether 5G wil... » read more

DAC Day Three: UVM, Machine Learning And DFT Come Together

By Brian Bailey - 08 Jun, 2016 - Comments: 0

The industry and users have a love/hate relationship with UVM. It has quickly risen to become the most used verification methodology and yet at the same time it is seen as being overly complex, unwieldy and difficult to learn. The third day of DAC gets started with breakfast with Accellera to discuss UVM and what we can expect to see in the next 5 years. The discussion was led by Tom Alsop, pri... » read more

Bridging the IP Divide

By Brian Bailey - 18 May, 2016 - Comments: 1

IP reuse enabled greater efficiency in the creation of large, complex SoCs, but even after 20 years there are few tools to bridge the divide between the IP provider and the IP user. The problem is that there is an implicit fuzzy contract describing how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to... » read more

Bridging The IP Divide

By Brian Bailey - 14 Apr, 2016 - Comments: 0

The adoption of an IP-based model has enabled designs to keep filling the available chip area while allowing design time to shrink. But there is a divide between IP providers and IP users. It is an implicit fuzzy contract about how the IP should be used, what capabilities it provides, and the extent of the verification that has been performed. IP vendors have been trying to formalize this as mu... » read more

The Week In Review: Design/IoT

By Jesse Allen - 08 Jan, 2016 - Comments: 0

EDA & IP EDA revenues increased 7.1% for Q3 2015, according to the EDA Consortium, upping the number to $1957.5 million, compared to $1828.1 million in Q3 2014. The four-quarters moving average also jumped by 8.8%. IC Physical Design & Verification saw the biggest gains, with a 14% increase compared to Q3 2014 and $407.9 million in revenue for the quarter. IP was runner up, with $652... » read more

HW Vs. SW: Who’s Leading Whom?

By Brian Bailey - 29 Oct, 2015 - Comments: 6

In the past, technologies were developed in the software world that have languished until they were taken up by the hardware community. Then they were refined and polished and became fully integrated into the hardware development and verification flow. Examples are lint and formal. That was followed by attempts to migrate methodologies, such as object-oriented programming, which is the basis fo... » read more

Blog Review: Sept. 9

By Ed Sperling - 09 Sep, 2015 - Comments: 0

Doulos' John Aynsley explains in a guest blog for Aldec why FPGA designers need to know SystemVerilog and UVM. Might be time to increase the coffee budget. Speaking of verification, Cadence's Frank Schirrmeister notes that his company is joining forces with Mentor Graphics and Breker for a contribution to the Accellera Portable Stimulus Working Group. This is potentially a big deal in veri... » read more

Silicon Catalyst: Semiconductor Incubator

By Ed Sperling - 26 Jan, 2015 - Comments: 0

Walk into any hall at CES this year and you're overwhelmed by the number of startups. Try doing the same at any semiconductor show, though, and the picture looks far different. Because of the startup capital required, and the amount of time it takes to see a return on investment, semiconductor entrepreneurs are having a much tougher time. Enter Silicon Catalyst, an incubator that was just st... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?