Fallout From Scaling

By Ed Sperling - 03 Feb, 2016 - Comments: 0

By Ed Sperling & Ann Steffora Mutschler Semiconductor scaling is becoming much more difficult and expensive at each new node, creating sharp divisions about what path to take next for which markets and applications. What used to be confined to one or two clear choices is now turning into a menu of items and possibilities, often with no clear guarantees for a successful outcome. Views ... » read more

Placing Bets On Future Technology

By Ed Sperling - 16 Nov, 2015 - Comments: 0

Marie Semeria, CEO of Leti, sat down with Semiconductor Engineering to talk about where the French research and technology organization is placing its future technology bets and what's behind those decisions. What follows are excerpts of that discussion. SE: It's becoming more difficult and expensive to shrink features, so where do we go next? Semeria: We see several areas that we believe... » read more

More Choices, Less Certainty

By Ed Sperling - 04 Nov, 2015 - Comments: 3

The increasing cost of feature scaling is splintering the chip market, injecting uncertainty into a global supply chain that has been continually fine-tuned for decades. Those with deep enough resources and a clear need for density will likely follow Moore's Law, at least until 7nm. What comes after that will depend on a variety of factors ranging from available lithography—EUV, multi-bea... » read more

Challenges At Advanced Nodes

By Ed Sperling - 09 Sep, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss finFETs, 22nm FD-SOI and how the how the market will segment over the next few years with Marie Semeria, CEO of [getentity id="22192" e_name="Leti"]; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Paul Boudre, CEO of Soitec; and Subramani Kengeri, vice president of global ... » read more

Challenges At Advanced Nodes

By Ed Sperling - 19 Aug, 2015 - Comments: 0

2.5D Creeps Into SoC Designs

By Ed Sperling - 13 Aug, 2015 - Comments: 0

A decade ago top chipmakers predicted that the next frontier for SoC architectures would be the z axis, adding a third dimension to improve throughput and performance, reduce congestion around memories, and reduce the amount of energy needed to drive signals. The obvious market for this was applications processors for mobile devices, and the first companies to jump on the stacked die bandwag... » read more

Which Process, Material, IP?

By Ed Sperling - 30 Jul, 2015 - Comments: 1

For years chipmakers have been demanding more choices. They've finally gotten what they wished for—so many possibilities, in fact, that engineering teams of all types are having trouble wading through them. And to make matters worse, some choices now come with unexpected and often unwanted caveats. At the most advanced nodes it's a given that being able to shrink features and double patter... » read more

Challenges At Advanced Nodes

By Ed Sperling - 23 Jul, 2015 - Comments: 1

Moore’s Law Reset?

By Ed Sperling - 13 Jul, 2015 - Comments: 0

GlobalFoundries today took the wraps off its 22nm FD-SOI process, promising to extend Moore's Law technologically without altering the economic equation—at least for the next couple of process nodes. Subramani Kengeri, vice president of global design solutions at [getentity id="22819" comment="GlobalFoundries"], said 22nm FD-SOI will provide the same 30% improvement in PPA that has been c... » read more

The Search For The Next Transistor

By Mark LaPedus - 20 Feb, 2014 - Comments: 3

In the near term, the leading-edge chip roadmap looks fairly clear. Chips based on today’s finFETs and planar fully depleted silicon-on-insulator (FDSOI) technologies are expected to scale down to the 10nm node. But then, the CMOS roadmap becomes foggy at 7nm and beyond. The industry has been exploring a number of next-generation transistor candidates, but suddenly, a few technologies are ... » read more

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tag: Leti

Fallout From Scaling

Placing Bets On Future Technology

More Choices, Less Certainty

Challenges At Advanced Nodes

Challenges At Advanced Nodes

2.5D Creeps Into SoC Designs

Which Process, Material, IP?

Challenges At Advanced Nodes

Moore’s Law Reset?

The Search For The Next Transistor