Hardware Security: One-Key Premise of Logic Locking


A new technical paper titled "Late Breaking Results: On the One-Key Premise of Logic Locking" was published by researchers at Synopsys. Abstract "The evaluation of logic locking methods has long been predicated on an implicit assumption that only the correct key can unveil the true functionality of a protected circuit. Consequently, a locking technique is deemed secure if it resists a good ... » read more

HW Security: Flip-Flops Along Logic Gates to Prevent Synthesis Tools’ Structural Leakages (TU Dresden, Ruhr Univ. Bochum)


A new technical paper titled "Flip-Lock: A Flip-Flop-Based Logic Locking Technique for Thwarting ML-based and Algorithmic Structural Attacks" was published by researchers at TU Dresden and Ruhr University Bochum. Abstract "Machine learning (ML) and algorithmic structural attacks have highlighted the possibility of utilizing structural leakages of an obfuscated circuit to reverse engineer th... » read more

New Type Of Hardware Trojans Based On Logic Locking


A technical paper titled “Logic Locking based Trojans: A Friend Turns Foe” was published by researchers at University of Maryland and University of Florida. Abstract: "Logic locking and hardware Trojans are two fields in hardware security that have been mostly developed independently from each other. In this paper, we identify the relationship between these two fields. We find that a com... » read more

Logic Locking at the RTL, Leveraging The Behavioral State Transition Coding For Obfuscation (University of Florida)


A new technical paper titled "ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM Approach" was published by researchers at University of Florida, Gainesville, FL. Abstract: "Hardware obfuscating is a proactive design-for-trust technique against IC supply chain threats, i.e., IP piracy and overproduction. Many studies have evaluated numerous techniques for obfuscation purposes. Neverth... » read more

RSFQ Logic Based Logic Locking Technique For Immunizing Against SAT-Based Attacks


A new technical paper titled "C-SAR: SAT Attack Resistant Logic Locking for RSFQ Circuits" was published (preprint) by researchers at University of Southern California. Abstract: "Since the development of semiconductor technologies, exascale computing and its associated applications have required increasing degrees of efficiency. Semiconductor-transistor-based circuits (STbCs) have strugg... » read more

U. Of Florida: Protecting Chip-Design IP From Reverse-Engineering


New research paper titled "Hardening Circuit-Design IP Against Reverse-Engineering Attacks" from University of Florida. "Design-hiding techniques are a central piece of academic and industrial efforts to protect electronic circuits from being reverse-engineered. However, these techniques have lacked a principled foundation to guide their design and security evaluation, leading to a long line... » read more

Novel Analog Key Generation Approach As An Alternative to Conventional Binary Keys (pHGen)


New research paper titled "pHGen: A pH-Based Key Generation Mechanism Using ISFETs" from RWTH Aachen University. Abstract "Digital keys are a fundamental component of many hardware- and software-based security mechanisms. However, digital keys are limited to binary values and easily exploitable when stored in standard memories. In this paper, based on emerging technologies, we introduce... » read more

Advances in Logic Locking: Past, Present, and Prospects


Abstract: "Logic locking is a design concealment mechanism for protecting the IPs integrated into modern System-on-Chip (SoC) architectures from a wide range of hardware security threats at the IC manufacturing supply chain. Logic locking primarily helps the designer to protect the IPs against reverse engineering, IP piracy, overproduction, and unauthorized activation. For more than a decade,... » read more

The Key is Left under the Mat: On the Inappropriate Security Assumption of Logic Locking Schemes


Abstract: "Logic locking has been proposed as an obfuscation technique to protect outsourced IC designs from IP piracy by untrusted entities in the design and fabrication process. In this case, the netlist is locked by adding extra key-gates, and will be unlocked only if a correct key is applied to the key-gates. The key is assumed to be written into a non-volatile memory after the fabricati... » read more