tag: low-power design

Reducing Software Power
By Brian Bailey - 12 Sep, 2019 - Comments: 0

With the slowdown of Moore's Law, every decision made in the past must be re-examined to get more performance or lower power for a given function. So far, software has remained relatively unaffected, but it could be an untapped area for optimization and enable significant power reduction. The general consensus is that new applications such as artificial intelligence and machine learning, whe... » read more

Moving Beyond Assertions: An Innovative Approach to Low-Power Checking Using UPF Tcl Apps
By Mentor, a Siemens Business - 11 Sep, 2019 - Comments: 0

This paper uses examples and case studies to demonstrate how to leverage UPF 3.0 information model TCL query functions (aka Tcl Apps) and tool provided CLI commands to do low-power checking of a design. This is an innovative way to dynamically verify the low-power intent after simulation has completed and all waveforms are available. The paper also explains how users can write their own checker... » read more

Taking Energy Into Account
By Ann Mutschler - 28 Aug, 2019 - Comments: 1

Considering power throughout the SoC design flow is common practice. The same cannot be said for energy, although that is beginning to change as chips increasingly incorporate heterogeneous processing elements. Combined with this, AI/ML/DL technologies increasingly allow engineering teams to explore and optimize design data for more targeted and efficient systems. But this approach also requ... » read more

Power Modeling Standard Released
By Brian Bailey - 14 Aug, 2019 - Comments: 0

Power is becoming a more important aspect of semiconductor design, but without an industry standard for power models, adoption is likely to be slow and fragmented. That is why Si2 and the IEEE decided to do something about it. Back in 2014, the IEEE expanded its interest in power standards with the creation of two new groups IEEE P2415 - Standard for Unified Hardware Abstraction and Layer fo... » read more

Optimizing Power For Learning At The Edge
By Brian Bailey - 08 Aug, 2019 - Comments: 0

Learning on the edge is seen as one of the Holy Grails of machine learning, but today even the cloud is struggling to get computation done using reasonable amounts of power. Power is the great enabler—or limiter—of the technology, and the industry is beginning to respond. "Power is like an inverse pyramid problem," says Johannes Stahl, senior director of product marketing at Synopsys. "T... » read more

Determining Where Power Analysis Matters Most
By Ann Mutschler - 08 Aug, 2019 - Comments: 0

How much accuracy is required in every stage of power analysis is becoming a subject of debate, as engineering teams wrestle with a mix of new architectures, different use cases and increasing pressure to get designs out on time. The question isn't whether power is a critical factor in designs anymore. That is a given. It is now about the most efficient way to tackle those issues, as well as... » read more

DRAM Tradeoffs: Speed Vs. Energy
By Ed Sperling - 31 Jul, 2019 - Comments: 1

Semiconductor Engineering sat down to talk about new DRAM options and considerations with Frank Ferro, senior director of product management at Rambus; Marc Greenberg, group director for product marketing at Cadence; Graham Allan, senior product marketing manager for DDR PHYs at Synopsys; and Tien Shiah, senior manager for memory marketing at Samsung Electronics. What follows are excerpts of th... » read more

Inferencing At The Edge
By Ed Sperling - 31 Jul, 2019 - Comments: 0

David Fritz, head of corporate strategic alliances at Mentor, a Siemens Business, shows how to apply YOLO (you only look once) at the edge, allowing automotive companies to move from a GPU to a much more efficient processor. That allows inferencing to move much closer to the sensor, so neural networks can be tailored to the type of data being produced. From there the data can be abstracted and ... » read more

Hardware-Software Co-Design Reappears
By Brian Bailey - 25 Jul, 2019 - Comments: 1

The core concepts in hardware-software co-design are getting another look, nearly two decades after this approach was first introduced and failed to catch on. What's different this time around is the growing complexity and an emphasis on architectural improvements, as well as device scaling, particularly for AI/ML applications. Software is a critical component, and the more tightly integrate... » read more

Power Is Limiting Machine Learning Deployments
By Brian Bailey - 25 Jul, 2019 - Comments: 3

The total amount of power consumed for machine learning tasks is staggering. Until a few years ago we did not have computers powerful enough to run many of the algorithms, but the repurposing of the GPU gave the industry the horsepower that it needed. The problem is that the GPU is not well suited to the task, and most of the power consumed is waste. While machine learning has provided many ... » read more

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