tag: low-power design

Focus Shifting To Photonics
By Ed Sperling - 17 Aug, 2016 - Comments: 4

Silicon photonics finally appears ready for prime time, after years of unfulfilled expectations and a vision that stretches back at least a couple decades. The biggest challenge has been the ability to build a light source directly into the silicon process, rather than trying to add one onto a chip after manufacturing. [getentity id="22846" e_name="Intel"] today said it has achieved that mi... » read more

Optimization Challenges For 10nm And 7nm
By Brian Bailey - 17 Aug, 2016 - Comments: 0

Optimization used to be a simple timing against area tradeoff but not anymore. As we go to each new node, the tradeoffs become more complicated involving additional aspects of the design that used to be dealt with in isolation. Semiconductor Engineering sat down to discuss these issues with Krishna Balachandran, director of product management for low power products at [getentity id="22032" ... » read more

Reaching The Power Budget
By Ann Mutschler - 11 Aug, 2016 - Comments: 1

Everything related to power in chip design today is a big deal—and it’s just getting bigger. Meeting the power budget is becoming harder at each new node, but it's also becoming difficult in a number of new application areas at existing nodes. That's a big problem because [getkc id="108" kc_name="power"] is now considered a competitive advantage in many markets. It's also one of the most... » read more

Mixed-signal/Low-power Design
By Jeff Dorsch - 03 Aug, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss mixed-signal/low-power IC design with Phil Matthews, director of engineering at Silicon Labs; Yanning Lu, director of analog IC design at Ambiq Micro; Krishna Balachandran, director of low power solutions marketing at [getentity id="22032" comment="Cadence"]; Geoffrey Ying, director of product marketing, AMS Group, [getentity id="22035" e_name="Syno... » read more

Mixed-signal/Low-power Design
By Jeff Dorsch - 26 Jul, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss mixed-signal/low-power IC design with Phil Matthews, director of engineering at Silicon Labs; Yanning Lu, director of analog IC design at Ambiq Micro; Krishna Balachandran, director of low power solutions marketing at [getentity id="22032" comment="Cadence"]; Geoffrey Ying, director of product marketing, AMS Group, [getentity id="22035" e_name="Syno... » read more

Energy-Efficient Design Helps Autonomous Vehicles Take Off
By Margaret Schmitt - 18 Jul, 2016 - Comments: 1

A new flight endurance record was set recently by the Predator B/MQ-9 Reaper Big Wing experimental drone, traveling 37 hours non-stop, and setting the bar for the next stage of autonomous flight development. The growth of drone technology and their autonomous capabilities for surveillance, security, and reconnaissance has grown rapidly over the past several years, thanks to ever-increasing perf... » read more

Implementation Limits Power Optimization
By Ann Mutschler - 14 Jul, 2016 - Comments: 3

Implementation is still the step that makes or breaks power budgets in chip design, despite improvements in power estimation, power simulations, and an increase in the number of power-related architectural decisions. The reason: All of those decisions must be carried throughout the design flow. “If implementation decides to give up, then it doesn't really matter at the end of the day,” s... » read more

Mixed-Signal/Low-Power Design
By Jeff Dorsch - 14 Jul, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss mixed-signal/low-power IC design with Phil Matthews, director of engineering at Silicon Labs; Yanning Lu, director of analog IC design at Ambiq Micro; Krishna Balachandran, director of low power solutions marketing at [getentity id="22032" comment="Cadence"]; Geoffrey Ying, director of product marketing, AMS Group, [getentity id="22035" e_name="Syno... » read more

Addressing Process Variation And Reducing Timing Pessimism At 16nm And Below
By Cadence - 13 Jul, 2016 - Comments: 0

At 16nm and below, on-chip variation (OCV) becomes a critically important issue. Increasing process variation makes a larger impact on timing, which becomes more pronounced in low-power designs with ultra-low voltage operating conditions. In this paper, we will discuss how a new methodology involving more accurate library characterization and variation modeling can reduce timing margins in libr... » read more

Executive Insight: Grant Pierce
By Ed Sperling - 29 Jun, 2016 - Comments: 0

Grant Pierce, president and CEO of Sonics, sat down with Semiconductor Engineering to discuss new ways to increase energy efficiency in SoCs. What follows are excerpts of that conversation. SE: Looking out at the semiconductor industry there are a lot of changes underway right now. What are the biggest impacts from your perspective? Pierce: The amount of data that is being captured or sen... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy