tag: M3D

HW Security: 2.5D and 3D Technologies Provide Opportunities in Designing Secure Systems (UCSB, Columbia)
By Technical Paper Link - 05 Sep, 2025 - Comments: 0

A new technical paper titled "Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges" was published by researchers at the University of California, Santa Barbara and Columbia University. Abstract "3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealin... » read more

Scheduling Architecture Integrated With M3D BEOL Memories For LLM Inference (Georgia Tech, Samsung)
By Technical Paper Link - 19 Aug, 2025 - Comments: 0

A new technical paper titled "Architecting Long-Context LLM Acceleration with Packing-Prefetch Scheduler and Ultra-Large Capacity On-Chip Memories" was published by researchers at Georgia Institute of Technology and Samsung. Abstract "Long-context Large Language Model (LLM) inference faces increasing compute bottlenecks as attention calculations scale with context length, primarily due to t... » read more

Novel Thin Film Growth Technique Of A WBG Sulfide Semiconductor in BEOL Compatible Conditions (USC, LBNL, TSMC)
By Technical Paper Link - 14 May, 2025 - Comments: 0

A new technical paper titled "Textured growth and electrical characterization of Zinc Sulfide on back-end-of-the-line (BEOL) compatible substrates" was published by researchers at USC, Lawrence Berkeley National Laboratory and TSMC. Abstract "Scaling of transistors has enabled continuous improvements in logic device performance, especially through materials engineering. However, surpassing ... » read more

Design-Space Analysis of M3D FPGA With BEOL Configuration Memories (Georgia Tech, UCLA)
By Technical Paper Link - 17 Jan, 2025 - Comments: 0

A new technical paper titled "Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories" was published by researchers at Georgia Tech and UCLA. Abstract "This work presents a novel monolithic 3D (M3D) FPGA architecture that leverages stackable back-end-of-line (BEOL) transistors to implement configuration memory and pass gates, significantly improving area, latency, and power ef... » read more

Scalability of Nanosheet Oxide FETs for Monolithic 3-D Integration
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "High-Field Transport and Statistical Variability of Nanosheet Oxide Semiconductor FETs With Channel Length Scaling" was published by researchers at The University of Tokyo and Nara Institute of Science and Technology. Abstract "We have investigated the scaling potential of nanosheet oxide semiconductor FETs (NS OS FETs) for monolithic 3-D (M3D) integration in t... » read more

Investigating The Ru/Ta Bilayer As An Alternative EUV Absorber To Mitigate Mask 3D Effects
By Technical Paper Link - 28 Aug, 2023 - Comments: 0

A technical paper titled “Ru/Ta bilayer approach to EUV mask absorbers: Experimental patterning and simulated imaging perspective” was published by researchers at KU Leuven and imec. Abstract: "The optical properties and geometry of EUV mask absorbers play an essential role in determining the imaging performance of a mask in EUV lithography. Imaging metrics, including Normalized Imag... » read more

Redesigning Core and Cache Hierarchy For A General-Purpose Monolithic 3D System
By Technical Paper Link - 24 Oct, 2022 - Comments: 0

A technical paper titled "RevaMp3D: Architecting the Processor Core and Cache Hierarchy for Systems with Monolithically-Integrated Logic and Memory" was published by researchers at ETH Zürich, KMUTNB, NTUA, and University of Toronto. Abstract: "Recent nano-technological advances enable the Monolithic 3D (M3D) integration of multiple memory and logic layers in a single chip with fine-graine... » read more

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy