Old Problem, New Solutions


By Ann Steffora Mutschler Electromigration (EM) and electrostatic discharge (ESD) may not be new, but design design sophistication and tiny wires are demanding that engineering teams take a fresh look and utilize new tools to lesson the impacts of damaging electrical events. “These are certainly not new phenomenon,” said Carey Robertson, director of product marketing for Calibre at Ment... » read more

Traversing The Abstraction Landscape


By Ann Steffora Mutschler Back in the early days of semiconductor design engineers could count the number of transistors on their chip with their own two eyes. They designed and worked at the same level of design abstraction when doing the timing analysis. Tools were SPICE-like, maybe abstracted with slightly simpler timing models than the SPICE-level transistor models. Thanks to Moore’... » read more

Intel’s Hot New Tri-Gate Processors


By Barry Pangrle Intel announced its newest third-generation Core processors on April 23rd. There has been much anticipation surrounding these new chips from Intel, largely because of their new 22nm tri-gate process technology used to fabricate these devices. Figure 1, from the presentation entitled, “Intel’s Revolutionary 22nm Transistor Technology,” by Mark Bohr and Kaizad Mistry, s... » read more

Experts At The Table: Hardware-Software Co-Design


By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, directo... » read more

Anchors Away – Anchoring and Seeding in Double Pattern Design.


David Abercrombie Many aspects of how double patterning (DP) affects the designer depend on the methodology used and the level of control the designer wants. One extreme in methodology and control is full two-layer design, in which the designer decomposes the entire design and tapes out two masks. The designer has complete control of the coloring, but all the responsibility and work as well. T... » read more

Experts At The Table: Hardware-Software Co-Design


By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, directo... » read more

Gap Vs. Gap


By Ed Sperling Among tools vendors it’s been standard practice to listen closely to customers but not deliver everything they ask for—or at least not always on the customers’ timetable. This strategy has worked well enough for both sides in the past, but at 20nm and in stacked die configurations, the level of tension between these two worlds is increasing, and the gaps in the tool cha... » read more

Rethinking Timing Optimization


By Ann Steffora Mutschler As semiconductor manufacturing technology continues its march toward 20nm, SoCs are plagued with advanced interconnect delays, cross capacitance, and process variability, as well as area and power constraints—and the significance of these factors is increasing with each passing node. “With lower nodes we are getting advantage on area, more and more logic is get... » read more

From Cryptic Error Messages To Contradictory Commands


By Ann Steffora Mutschler For the past 30 years, semiconductor designers have increasingly relied on automated CAD tools to complete their projects. Over time, these tools have indeed improved from a functionality perspective, but sometimes usability has not kept up with users’ needs. Depending on which tools and what type of use, some tools are easier to use than others, according to Mik... » read more

Boosting Yield With Layout Awareness


By Ann Steffora Mutschler Yield. Just the word can make many engineers cringe and hide in their cubicles—especially with manufacturing problems and excessive power during test increasing causing failures. But the combination of physical data with diagnostics engines may be the light at the end of the tunnel, allowing for easier pinpointing of defects. There are many reasons why a chip fai... » read more

← Older posts Newer posts →