Streamlining Complex Semiconductor Designs With IP-XACT-Based Structured Assembly

By Insaf Meliane - 29 Aug, 2024 - Comments: 0

Semiconductor design is rapidly evolving because technologies such as AI and machine learning (ML) applications push the boundaries of complexity and specialization. Modern chips require hundreds or thousands of IP blocks, leading to significant design challenges. Multi-die architectures, which distribute functional blocks across multiple dice, demand expert planning to ensure connectivity and ... » read more

Design Tool Think Tank Required

By Brian Bailey - 29 Feb, 2024 - Comments: 1

When I was in the EDA industry as a technologist, there were three main parts to my role. The first was to tell customers about new technologies being developed and tool extensions that would be appearing in the next release. These were features they might find beneficial both in the projects they were undertaking today, and even more so, would apply to future projects. Second, I would try and ... » read more

The End Of Closed EDA

By Brian Bailey - 22 Sep, 2022 - Comments: 0

In a previous life, I was a technologist for a large EDA company. One of my primary responsibilities in that position involved talking to a lot of customers to identify their pain points, and what new tools we could develop that would ease their problems. You would think that would be an easy task, but it certainly was not the case. For example, if you ask a developer what their biggest frus... » read more

A New Breed Of EDA Required

By Brian Bailey - 23 Jun, 2022 - Comments: 1

While doing research for one of my stories this month, a couple of people basically said that applying methodologies of the past to the designs of today can be problematic because there are fundamental differences in the architectures and workloads. While I completely agree, I don't think these statements go far enough. Designs of today generally have one of everything — one CPU, one accel... » read more

Shifting The Design Paradigm To Improve Verification Efficiency

By Harry Foster - 10 Mar, 2022 - Comments: 0

We are in the midst of a verification crisis manifested by a growing gap between verification efficiency and effectiveness. This crisis cannot be solved through improvements in verification methodologies and techniques alone. Indeed, it requires a philosophical change in the way we approach design, with an emphasis on bug prevention. We refer to this fundamental change as design using intent-fo... » read more

A Price To Be Paid

By Brian Bailey - 27 May, 2021 - Comments: 1

Ancient wisdom says you should be careful what you ask for, because you just might get it. This was certainly true many times during my career within EDA, and I am sure it is still happening today. Sometimes the outcome was not what was wanted, or the price was higher than expected. As an example, consider VHDL, the language that was meant to correct the problems of Verilog. One of the probl... » read more

Invent A New Way To Do Your Job

By Hagai Arbel - 27 May, 2021 - Comments: 0

My friends own a farm in the southwest of France, and though I spent most of my recent decades around big cities, my village-raised roots are sending me working in the fields every time I have the time. I don’t really care what I’m assigned to, as long as soil, the nearby forest trees, and the sky (preferably blue) will take part. If the job consists of repeating actions, I like to come up ... » read more

Stuck In A Rut

By Brian Bailey - 25 Mar, 2021 - Comments: 4

In the DVCon panel session about open-source verification, the first part of which has been published along with this blog, you will read about a fiery debate between the panelists. This is regarding the ability of the EDA industry to innovate. On one side is the accusation that there has been no real innovation since 1988. On the other side, there have been fantastic advances have been made th... » read more

A New Method For Electrical Systems Design

By Nigel Hughes - 03 Dec, 2020 - Comments: 0

Electrical system complexity is reaching a tipping point across industries, from modern passenger vehicles to sophisticated industrial machines that can now contain nearly 5,000 wiring harnesses. The electrical systems of these machines contain multiple networks, thousands of sensors and actuators, miles of wiring and tens of thousands of discrete components (figure 1). Designing these complex ... » read more

Verification Convergence: Problem Definition

By Hagai Arbel - 30 Nov, 2020 - Comments: 0

A while ago, I had to go to the ER with my friend who suddenly had a numb feeling in his face. He felt okay (and everything else is okay with him), but better be safe than sorry. While the doctor examined him I noticed that before tracing the problem itself, she asked some questions to rule-out a problem she was already familiar with and that can manifest itself in similar ways. Only then, a... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?