tag: methodologies

Customizing Low-Power Platforms Using UPF Dynamic Properties
By Progyna Khondkar - 12 Nov, 2020 - Comments: 0

Low power design and verification engineers need a way to continuously probe various dynamic properties of UPF objects in order to monitor the current state of a verification strategy and utilize that information to develop custom low-power verification environments. Unfortunately, there hasn’t been a reliable, formalized way to do this. Since availability of the dynamic properties of unif... » read more

Clarifying Language/Methodology Confusion
By Aldec - 28 Oct, 2020 - Comments: 0

Engineers working on modern, large FPGA designs face multiple challenges: changing languages, methodologies and tools implementing them. The fact that many designs now contain both hardware and software only add to the confusion. This document tries to clarify the situation. Click here to read more. » read more

Importance Of A Functional Verification Methodology
By Shubhodeep Roy Choudhury - 24 Sep, 2020 - Comments: 0

A good functional verification methodology is extremely crucial to the success of any semiconductor design project. Missed or late bugs can massively hurt market share, revenue, and brand name even for reputed companies. The complexity of SoC designs along with tight time-to-market constraints demand high levels of efficiency in the verification process. The approach to verify the functional... » read more

Methodology Vs. Problem-Solving
By Hagai Arbel - 22 Jul, 2020 - Comments: 1

When I was 18, I bought a Vespa ’67: the famous Italian scooter. It was already very old then, totally beaten-up, but luckily I had a friend who owned an auto-repair shop, and he was kind enough to give me some access at night. For several weeks, I taught myself the art of metal bodywork, ending up with a beautiful metallic sky-blue ‘67 Vespa. God, I loved that machine! Then one day, ... » read more

Analog Design Needs To Change
By Dave Reed - 23 Apr, 2020 - Comments: 0

It’s an exciting time to be involved in analog design! Innovation in analog design methodology has been flourishing with the introduction of new tools and improved methodologies. And this innovation is badly needed; analog design is getting tougher. Design schedules remain tight, and the technical challenges analog designers face continue to grow – especially when moving to advanced node te... » read more

Three Steps To Faster Low Power Coverage Using UPF 3.0 Information Models
By Madhur Bhargava - 16 Jan, 2020 - Comments: 2

Controlling power has its costs. The added power elements and their interactions make verification of low-power designs much more difficult and the engineer’s job overwhelmingly complex and tedious. Early versions of the Unified Power Format (UPF) provided some relief, but lacked provisions for a standardized methodology for low-power coverage. Ad hoc approaches are error prone and highly ... » read more

Spreadsheets In Virtuoso
By Srinath Anantharaman - 07 Oct, 2019 - Comments: 0

The looming tape-out deadline is the nightmare that keeps most design managers up at night. Managing schedules and tracking progress is always a black art that few, if any, can master. Various project management tools and methodologies have been developed that can help, if followed diligently. However, the learning curve of the tools, or the training and overhead of the process, often result in... » read more

Writing Reusable UPF For RTL And Gate-Level Low Power Verification
By Durgesh Prasad - 08 Aug, 2019 - Comments: 0

By Durgesh Prasad, Jitesh Bansal and Madhur Bhargava The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, and finally during place and route. A major problem is that the UPF needs to be refined or modified at every stage to keep it compatible ... » read more

ASIC/IC Trends With A Focus On Factors Of Silicon Success
By Harry Foster - 09 May, 2019 - Comments: 0

“The more you know, the more you know you don't know.” ― Aristotle, 4th C. BC When Aristotle uttered this humble aphorism, he wasn’t telling us to throw up our hands and not bother with learning. He was encouraging us to continue digging deeper, to get answers and ask questions of those answers — that the thrills and rewards of study are truly without end. This is a big part of ou... » read more

Trends In FPGA Verification Effort And Adoption: The 2018 Wilson Research Group Functional Verification Study
By Harry Foster - 14 Mar, 2019 - Comments: 0

As contributors and pioneers in the digital revolution, we are often so busy creating and innovating that we are compelled to focus on the trees, never mind the forest. But as we are all aware, the more we know about the bigger picture, context, historical and projected trends, or simply how other people are doing the same thing, the more efficiently and successfully we can do our jobs. Prov... » read more

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