tag: Mimasic

Power Shifts In Digital Chip Space
By Bhanu Kapoor - 08 Aug, 2013 - Comments: 0

By Bhanu Kapoor The power issue has been quite disrupting in the digital semiconductor space. The processor architecture shifted to parallel processing with the “power wall” stopping the frequency scaling that the industry had conveniently used in the last few decades. The power issue also is causing semiconductor process technology to change in ways other than simply scaling from one ... » read more

What’s Missing In Low-Power Verification
By Ed Sperling - 09 May, 2013 - Comments: 0

By Ed Sperling Ask two engineers what low-power verification is and you’ll likely get the same checklist that includes confidence in the overall design, good coverage, a long list of corner cases, and other items in a checklist. Ask them how to reach that goal you’ll almost certainly get different answers—or maybe no answers at all. Power has emerged as a ubiquitous concern in design,... » read more

Improved Efficiency
By Bhanu Kapoor - 11 Apr, 2013 - Comments: 0

By Bhanu Kapoor We constantly hear about process technology advances and their impact on power consumption of ICs, but the power management techniques have remained the same over last few process technology generations. Power gating, dynamic voltage and frequency scaling, and threshold voltage scaling have been the key power management techniques since the 90nm process technology. Clock gating... » read more

Near-Threshold Computing
By Bhanu Kapoor - 13 Sep, 2012 - Comments: 0

By Bhanu Kapoor There were two main contributing factors to power becoming a big problem ("The Power Wall") starting around the 65nm process technology. First, the fast-growing leakage component became as significant as the dynamic power. Second, the scaling of the supply voltage stopped around 1.1 volts. Process technology advances such as HKMG and 3D tri-gate transistors have enabled con... » read more

The Bigger Problem
By Bhanu Kapoor - 10 May, 2012 - Comments: 0

By Bhanu Kapoor Getting power management features already built into chips to be fully utilized is indeed the bigger problem. The features here refer to hooks provided by power management techniques such as voltage and frequency scaling, power gating, and threshold voltage scaling. There is no doubt that these features have helped a lot in optimizing power consumption. But they are mainly a... » read more

Intel’s Power Play
By Bhanu Kapoor - 08 Mar, 2012 - Comments: 0

By Bhanu Kapoor With the Ivy Bridge processor, Intel claims half the power at the same performance level or double the performance with the same power consumption as the Sandy Bridge processor. The implications of 2X performance-per-watt improvement will be significant for server, desktop, laptop, tablet, and smart phone applications. You can be operating at the same frequency while either... » read more

Powerbenches
By Bhanu Kapoor - 08 Sep, 2011 - Comments: 0

By Bhanu Kapoor Today, in the era of IPs and SoCs, verification consumes up to 70% of the design effort. Most of the rest of the design effort is focused on iterations related to meeting the performance goals. We also hear that power has become the No. 1 design criteria for several categories of semiconductor devices, but we still lack well-defined, power-oriented methodologies and tools that ... » read more

5 Ways To Cut Power
By Ed Sperling - 16 Jun, 2011 - Comments: 0

By Ed Sperling Low energy consumption with minimal leakage has emerged as the most competitive element in an IC design, regardless of whether it involves a plug, a battery, or whether it’s powered by a gasoline engine. While components on an SoC aren’t always power-aware, they’ll have to be in the future as consumers focus first on energy efficiency. With rising fuel costs, a concern ... » read more

Low-Power Solutions At DAC
By Bhanu Kapoor - 16 Jun, 2011 - Comments: 0

By Bhanu Kapoor Power is the main driver of semiconductor process technology related advances recently. One would expect a similar focus in the electronic design automation industry to help designers implement low power designs. However, the latest DAC in San Diego didn’t give the impression that the EDA industry is thinking likewise, perhaps with the exception of verification aspects of low... » read more

Fire In The Hole?
By Bhanu Kapoor - 14 Apr, 2011 - Comments: 0

By Bhanu Kapoor At the 2001 ISSCC, Pat Gelsinger, then Senior VP at Intel, had observed the following in connection with the growing issue of chip power density: “Ten years from now microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second—about the same number of calculations that the world's fastest supercomputer can perform now. Unfortunate... » read more

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