tag: Mimasic

Experts At The Table: Low-Power Management And Verification
By Ed Sperling - 11 Mar, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering moderated a panel featuring Bhanu Kapoor, president of Mimasic; John Goodenough, director of design technology at ARM; and Prapanna Tiwari, CAE manager at Synopsys. What follows are excerpts of their presentations, as well as the question-and-answer exchange that followed. Bhanu Kapoor: There are two types of power you need to consider: Dynamic power, ... » read more

Is Power-Aware Simulation A Must-Have?
By Bhanu Kapoor - 12 Nov, 2009 - Comments: 0

By Bhanu Kapoor Is power-aware simulation-based verification necessary? This question has been frequently asked by the designers and becomes even more important in the context of potentially increased costs for simulation, with or without the recessionary environment. Those contending that it is not a must-have point to: --Power-managed designs were being done even when ... » read more

Power Delivery Issues
By Ed Sperling - 10 Nov, 2009 - Comments: 0

By Ed Sperling Reducing the voltage in a system on chip is like turning down the water pressure on a home plumbing system. Pretty soon you find out that not all the faucets work properly because there isn’t enough pressure behind them. While it’s vital to drop the voltage to boost battery life in mobile devices, not to mention reduce the overall power consumption in plug-in devices, t... » read more

Understanding Power-Aware Verification
By Bhanu Kapoor - 10 Jun, 2009 - Comments: 0

By Bhanu Kapoor We are at the crossroads of some fundamental changes that are taking place in the semiconductor industry. Power consumption has become one of the most important differentiating factors for semiconductor products due to a major shift in the market towards handheld consumer devices. Power is a primary design criterion for the bulk of semiconductor designs now, and it's a key re... » read more

Lower Power, Bigger Problems
By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Low power used to be an afterthought in semiconductor design, and it almost was never a consideration in verification or manufacturability. But at each new process node, the number of power considerations goes up as the line widths go down. To begin with, there are two basic types of power. The first is dynamic, which has been a consideration ever since batteries were added int... » read more

Less Room For Error
By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Say goodbye to fat design margins in advanced SoCs. The commonly used method of adding extra performance or area into semiconductors to overcome variability in manufacturing processes or timing closure issues has begun to create problems of its own. While there was plenty of slack available at 90nm, adding margins at 45nm and 32nm disrupts performance or eats into an increasing... » read more

How Many Power Islands Is Too Many?
By Ed Sperling - 13 May, 2009 - Comments: 0

By Ed Sperling Power domains, also known as power islands, have become to design engineers what multiple cores are to processor architects. They can serve a purpose, namely reducing static current leakage and saving battery life. But they also can add so much complexity that they can make it almost impossible to get a new chip out the door. Just as there has been talk of hundreds of cores, th... » read more

On, Off and Mostly Off
By Ed Sperling - 13 Mar, 2009 - Comments: 0

<p>By Ed Sperling</p> <p>System-on-chip architecture has always been about getting the most performance out of a device, and the basic premise is that when you turn on a device it is always on.</p> <p>That approach has been challenged over the past few years with a fundamental shift toward more of the design being in the ‘off’ position. Aside from reversi... » read more

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