Lower Power, Bigger Problems

Static current leakage can be managed but never eliminated; verification continues to be a problem.


By Ed Sperling

Low power used to be an afterthought in semiconductor design, and it almost was never a consideration in verification or manufacturability. But at each new process node, the number of power considerations goes up as the line widths go down.

To begin with, there are two basic types of power. The first is dynamic, which has been a consideration ever since batteries were added into devices. Dynamic power is the amount of power needed to do something useful with a device. And while components continue to get more efficient, those improvements typically are measured in the single digits.

Much bigger gains come from more efficient use of those components, particularly turning them on and off. At 130nm and above, turning off components was a “nice to have.” Below 130nm, it’s a requirement because of static power consumption—the current that leaks out of transistors that are left in the “on” state when they’re not being used.

The effects are easy to see when nothing is done at different nodes versus remediation with power shutdowns, as the following diagrams show:




Source: Mimasic

Bhanu Kapoor, founder of Mimasic, a Richardson, Texas-based consultancy, said during a recent speech that there are several interdependencies in static leakage that need to be considered.

“Leakage has a linear relationship with the supply voltage,” Kapoor said. “Leakage also has sub-threshold and gate-tunneling components, which have been growing exponentially with respect to the threshold voltage. Gate tunneling is being addressed with high-k materials and metal gate technology. The sub-threshold component is still there.”

Old problem, new tricks

Addressing static leakage is absolutely essential at 90nm and beyond. Kapoor said that at 90nm, leakage amounts to 20% to 30% of the total power consumed by a device, and techniques such as clock gating have no impact on static leakage. The only thing that really has an effect is shutting down portions of a chip or device that are not in use. So while a cell phone also has a camera, games and music, the only function that has to be on all the time is the ability to receive calls.

“There is a strong dependence on power with respect to voltage, and there are several techniques to use voltage to get a handle on power consumption,” he said. “A typical application like a cell phone has times when you use applications and there are long periods of standby when the device is not in use.”

Voltage also can be scaled for a specific function or application of a cell phone, for example, something that is beginning to make its way into heterogeneous multicore design. The basic idea is that you have a fixed power budget for a design, and you can better utilize that budget if all the cores aren’t drawing the same voltage. A phone needs more power than the camera, for example, so the core design can be changed to reflect that. Similarly, logic and memory for one function may be significantly smaller than for another.

Verification challenges

But even after a design team has done everything to minimize power consumption, the problem is far from solved. Verification, which accounts for 70% of the time spent in chip design, gets significantly more complicated as each of these new tricks is implemented. There are now a lot of different power states in the design, and there are voltage islands that can be on, off, or somewhere in between. Intel, for example, has seven sleep states in its core processors.

“What all of these techniques did was introduce voltage as a variable in the design process,” Kapoor said. “Verilog and VHDL, or any other language, don’t have a notion of voltage as a variable. You need additional description to go along with the functional descriptions to describe the power management architecture. That has led to a power architecture description format that is being standardized through IEEE’s 1801 working group. But in terms verification, now that you are powering down different regions of the chip you need to isolate those and retain values when you are powering down. When you are going from one region to another you need to level shift these signals. And all of these things need to be validated.”

He said that requires protocols for shifting things on and off, potentially changing the design to allow for verification, and some formal assertions for when one area powers down and what effect it has on other areas of the design.

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