Problems In Testing AI Chips

By Ed Sperling - 20 May, 2025 - Comments: 0

As AI chips get larger, it becomes much harder to test them. Today, there can be as many as 22,000 pins on a 150mm² die, but in the future that number may increase to 80,000 pins. That creates a huge challenge for the fabs and the testers. Jack Lewis, chief technologist at Modus Test, talks about the intricacies of testing these complex devices, from maintaining contact with those pins even on... » read more

Coaxial Test Sockets Are In The Critical Path Of Advanced AI/CPU Products

By Jack Lewis - 08 May, 2025 - Comments: 0

Advanced AI/CPU processors demand extreme high frequency and power performance from SLT and ATE test sockets. These sockets are in the critical path at the end of a very costly silicon fabrication and advanced packaging manufacturing process. Yield loss at this point in the process is catastrophic to the bottom line. We at Modus Test, working in conjunction with our customers, have seen first-h... » read more

Nearly Invisible: Defect Detection Below 5nm

By Gregory Haley - 08 Apr, 2025 - Comments: 0

Detecting sub-5nm defects creates huge challenges for chipmakers, challenges that have a direct impact on yield, reliability, and profitability. In addition to being smaller and harder to detect, defects are often hidden beneath intricate device structures and packaging schemes. Moreover, traditional optical and electrical probing methods, trusted for decades, are proving inadequate against ... » read more

Big Changes Ahead For Interposers And Substrates

By Gregory Haley - 24 Mar, 2025 - Comments: 1

Interposers and substrates are undergoing a profound transformation from intermediaries to engineered platforms responsible for power distribution, thermal management, high-density interconnects, and signal integrity in the most advanced computing systems. This shift is being driven by AI, high-performance computing (HPC), and next-generation communications, where the need for heterogeneous ... » read more

Failure To Launch

By Gregory Haley - 11 Mar, 2025 - Comments: 1

Failure analysis (FA) is an essential step for achieving sufficient yield in semiconductor manufacturing, but it’s struggling to keep pace with smaller dimensions, advanced packaging, and new power delivery architectures. All of these developments make defects harder to find and more expensive to fix, which impacts the reliability of chips and systems. Traditional failure analysis techniqu... » read more

Simulation Closes Gap Between Chip Design Optimization And Manufacturability

By Gregory Haley - 11 Feb, 2025 - Comments: 0

Simulation is playing an increasingly critical and central role throughout the design-through-manufacturing flow, fusing together everything from design to manufacturing and test in order to reduce the number and cost of silicon respins. The sheer density of modern chips, combined with advanced packaging techniques like 3D stacking and heterogeneous integration, has made iterative physical p... » read more