tag: multi-die

Achieving Successful Multi-Die Signoff
By Vamsi Thatha - 19 Dec, 2024 - Comments: 0

Multi-die designs leveraging 2.5D and 3D technologies are becoming crucial for various electronics applications, including high-performance computing (HPC), artificial intelligence (AI), automotive, and mobile devices. These designs allow the integration of dies from different foundries and technology nodes, enhancing density and interconnect speeds beyond traditional discrete dies. However, th... » read more

Integrating Ethernet, PCIe, And UCIe For Enhanced Bandwidth And Scalability For AI/HPC Chips
By Madhumita Sanyal - 12 Dec, 2024 - Comments: 0

By Madhumita Sanyal and Aparna Tarde Multi-die architectures are becoming a pivotal solution for boosting performance, scalability, and adaptability in contemporary data centers. By breaking down traditional monolithic designs into smaller, either heterogeneous or homogeneous dies (also known as chiplets), engineers can fine-tune each component for specific functions, resulting in notable im... » read more

Analysis Of Multi-Chiplet Package Designs And Requirements For Production Test Simplification
By Vineet Pancholi - 21 Nov, 2024 - Comments: 1

In recent years there has been a sharp rise of multi-die system designs. Numerous publications targeting a large variety of applications exist in the public domain. One presentation [2] on the IEEE’s website does a good job of detailing the anecdotal path of multi-die systems by way of chiplet building blocks integrated within a single package [2]. The presentation includes references to a ha... » read more

Innovate Faster with A Multi-Die Solution
By Synopsys - 13 Nov, 2024 - Comments: 0

The semiconductor industry is experiencing a monumental shift in chip design, driven by the dramatic increase in AI compute performance requirements and limitations of Moore’s Law. The industry is adopting multi-die designs, which is the heterogeneous or homogeneous integration of dies (also called chiplets) in a single package. While multi-die design is the solution, it also introduces se... » read more

3DIO IP For Multi-Die Integration
By Lakshmi Jain - 17 Oct, 2024 - Comments: 0

By Lakshmi Jain and Wei-Yu Ma The demand for high performance computing, next-gen servers, and AI accelerators is growing rapidly, increasing the need for faster data processing with expanding workloads. This rising complexity presents two significant challenges: manufacturability and cost. From a manufacturing standpoint, these processing engines are nearing the maximum size that lithogra... » read more

Advancements In Silicon Device Technology And Design Driving New SLM Monitor Categories
By Ash Patel - 15 Oct, 2024 - Comments: 0

Silicon, the foundation of modern electronics, has seen continuous advancements since the early days of integrated circuits. The pace of innovation has been driven by the relentless quest for miniaturization, increased performance, and efficiency. However, Moore’s Law is no longer a given and silicon is facing functional limitations as technology scales. To address these challenges and conti... » read more

Simultaneous Bi-Directional Signaling: A Breakthrough Alternative For Multi-Die Assemblies
By Ramin Farjadrad - 29 Aug, 2024 - Comments: 0

In designing multi-die systems-in-package, with or without chiplets, it is easy to think of the interconnect between dies as simply analogous to the interconnect between functional blocks on a single die. But this analogy can lead architects and designers into a blind alley from which it becomes impossible to meet system performance and power requirements. The reason lies in fundamental differe... » read more

Enabling Efficient Multi-Die Design Implementation and IP Integration
By Synopsys - 28 Aug, 2024 - Comments: 0

Many industry trends are driving chip developers to consider multi-die designs using advanced 2.5D and 3D technologies. Such designs enable incorporating heterogeneous and homogeneous dies in a single package, increasing density while reducing signal propagation times. However, multi-die designs introduce new challenges that must be addressed by all relevant electronic design automation (EDA) a... » read more

Ensuring Multi-Die Package Quality And Reliability
By Faisal Goriawalla - 08 Aug, 2024 - Comments: 0

Multi-die designs are gaining broader adoption in a wide variety of end applications, including high-performance computing, artificial intelligence (AI), automotive, and mobile. Despite clear advantages, there are new challenges that need to be addressed for successful multi-die realization. This article gives a high-level overview of the multi-die test challenges that go beyond the design p... » read more

Are You Ready For HBM4? A Silicon Lifecycle Management (SLM) Perspective
By Faisal Goriawalla - 06 Aug, 2024 - Comments: 0

Many factors are driving system-on-chip (SoC) developers to adopt multi-die technology, in which multiple dies are stacked in a three-dimensional (3D) configuration. Multi-die systems may make power and thermal issues more complex, and they have required major innovations in electronic design automation (EDA) implementation and test tools. These challenges are more than offset by the advantages... » read more

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