Novel Assembly Approaches For 3D Device Stacks


The next big leap in semiconductor packaging will require a slew of new technologies, processes, and materials, but collectively they will enable orders of magnitude improvement in performance that will be essential for the AI age. Not all of these issues are fully solved, the recent Electronic Components Technology Conference (ECTC) provided a glimpse into the huge leaps in progress that ha... » read more

What’s Next For Through-Silicon Vias


From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

Backside Power Delivery Gears Up For 2nm Devices


The top three foundries plan to implement backside power delivery as soon as the 2nm node, setting the stage for faster and more efficient switching in chips, reduced routing congestion, and lower noise across multiple metal layers. The benefits of using this approach are significant. By delivering power using slightly fatter, less resistive lines on the backside, rather than inefficient fro... » read more