Chip Industry Week In Review

By The SE Staff - 02 Feb, 2024 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan. Cadence introduced an AI-based thermal stress and analysis platform aimed at 2.5D and 3D-ICs, and cooling for PCBs and electronic assemblies. The company also debuted a HW/SW accelerated digital twin solution for multi-physics system design and analysis, combining GPU-resident computational fluid dynamics (CFD) solvers with dedicated GPU hardwar... » read more

Technical Paper Round-Up: March 22

By Linda Christensen - 22 Mar, 2022 - Comments: 0

New memories, materials, and transistor types, and processes for making those devices, highlighted the past week's technical papers. That includes everything from vertical MoS2 to programmable black phosphorus image sensors and photonic lift-off processes for flexible thin-film materials. Papers continue to flow from all parts of the supply chain, with some new studies out of Pakistan, Seoul... » read more

Key Recovery for Content Protection Using Ternary PUFs Designed with Pre-Formed ReRAM

By Technical Paper Link - 19 Mar, 2022 - Comments: 0

RESEARCH PAPER Abstract "Physical unclonable functions, embedded in terminal devices, can be used as part of the recovery process of session keys that protect digital files. Such an approach is only valuable when the physical element offers sufficient tamper resistance. Otherwise, error correcting codes should be able to handle any variations arising from aging, and environmentally induce... » read more

Week in Review: IoT, Security, Auto

By Jeff Dorsch - 19 Oct, 2018 - Comments: 0

Internet of Things At Arm TechCon, Arm unveiled its Neoverse brand identity, providing an infrastructure foundation for 5G, the Internet of Things, edge computing, and other applications. The Arm Neoverse IP will proliferate next year from Arm and its technology partners. With Arm’s “Ares” platform, to be introduced in 2019, the company promises to deliver 30% per-generation performance ... » read more

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Northern Arizona University

Chip Industry Week In Review

Technical Paper Round-Up: March 22

Key Recovery for Content Protection Using Ternary PUFs Designed with Pre-Formed ReRAM

Week in Review: IoT, Security, Auto

Trending Articles

Hybrid Bonding Makes Strides Toward Manufacturability

Americas Chip Funding Energizes Industry

Advanced Packaging Driving New Collaboration Across Supply Chain

Chiplets Make Progress Using Interconnects As Glue

2D Semiconductors Make Progress, But So Does Silicon

Knowledge Centers
Entities, people and technologies explored

Related Articles

Partitioning In The Chiplet Era

3.5D: The Great Compromise

Legacy Process Nodes Going Strong

AI’s Role In Chip Design Widens, Drawing In New Startups

Key Technologies To Extend EUV To 14 Angstroms

Memory Fundamentals For Engineers

What Comes After HBM For Chiplets

Why Small Fab And Assembly Houses Are Thriving

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tag: Northern Arizona University

Chip Industry Week In Review

Technical Paper Round-Up: March 22

Key Recovery for Content Protection Using Ternary PUFs Designed with Pre-Formed ReRAM

Week in Review: IoT, Security, Auto

Trending Articles

Hybrid Bonding Makes Strides Toward Manufacturability

Americas Chip Funding Energizes Industry

Advanced Packaging Driving New Collaboration Across Supply Chain

Chiplets Make Progress Using Interconnects As Glue

2D Semiconductors Make Progress, But So Does Silicon

Knowledge Centers Entities, people and technologies explored

Related Articles

Partitioning In The Chiplet Era

3.5D: The Great Compromise

Legacy Process Nodes Going Strong

AI’s Role In Chip Design Widens, Drawing In New Startups

Key Technologies To Extend EUV To 14 Angstroms

Memory Fundamentals For Engineers

What Comes After HBM For Chiplets

Why Small Fab And Assembly Houses Are Thriving

Sponsors

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Knowledge Centers
Entities, people and technologies explored