The Trouble With Multicore Software

By Ed Sperling - 12 Feb, 2009 - Comments: 0

David Patterson, Professor of Computer Science at UC Berkeley, presented his views to the Naval Postgraduate School about the prospects for multicore programming success. This video was excerpted from his presentation. [youtube vid=EDHXIH8DlLY] » read more

Fewer Engineers Means Fewer Weapons Designs

By Ed Sperling - 22 Jan, 2009 - Comments: 0

By Ed Sperling Uncle Sam wants you—but not on the battlefield. The diminished pool of qualified engineering and science graduates is having a major impact on the defense market. There simply are too few trained engineers to design complex systems for the military at the rate they’re needed, creating a huge hole in a system that has been humming along for the better part of a century. And ... » read more

Case Study: A Better Way To Predict Weather

By Ed Sperling - 17 Dec, 2008 - Comments: 0

By Ed Sperling Most of our weather predictions are developed from about 150 stationary government radar systems, which interlock and occasionally overlap to create a cohesive picture. The picture isn’t perfect—in fact, it’s probably the equivalent of looking at a large, grainy satellite photo—which creates plenty of wrong forecasts. But the system can track large storms across state bo... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

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AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

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Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

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The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: NPS

The Trouble With Multicore Software

Fewer Engineers Means Fewer Weapons Designs

Case Study: A Better Way To Predict Weather