tag: Nvidia

Cars, Security, And HW-SW Co-Design
By Jeff Dorsch - 31 Aug, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss parallel hardware/software design with Johannes Stahl, director of product marketing, prototyping and FPGA, [getentity id="22035" e_name="Synopsys"]; [getperson id="11411" comment="Bill Neifert"], director of models technology, [getentity id="22186" comment="ARM"]; Hemant Kumar, director of ASIC design, Nvidia; and Scott Constable, senior member of ... » read more

Surprises At Hot Chips 2016
By Ed Sperling - 25 Aug, 2016 - Comments: 0

Who would have thought an Intel architect would be on stage talking about cutting pennies out of MCU prices? Or that Nvidia would be trumpeting an automotive SoC whose chief performance advantages come from the integration of ARM CPUs that can support up to eight virtual machines? Or that Samsung would be developing a quad-core mobile processor from scratch based on its own unique architecture?... » read more

Automotive Design Requires Rigor
By Ann Mutschler - 04 Aug, 2016 - Comments: 0

Playing in the automotive space means a significant investment in terms of resources, and it brings other challenges as well, not to mention the specific engineering challenges of ADAS. According to Mike Stellfox, a Cadence Fellow, the challenges are adding up for current Tier 2 suppliers. “Mostly what we see is the same kinds of customers — at least in the Tier 2s — for the hardware ... » read more

What’s Next For UVM?
By Brian Bailey - 28 Jul, 2016 - Comments: 0

The infrastructure for much of the chip verification being done today is looking dated and limited in scope. Design has migrated to new methodologies, standards and tools that are being introduced to deal with heterogeneous integration, more customization, and increased complexity. Verification methodologies started appearing soon after the release of SystemVerilog. Initially they were inten... » read more

China Tops Top500
By Barry Pangrle - 14 Jul, 2016 - Comments: 0

The last time I wrote about the Green500, the Chinese machine Tianhe-2 was at the top of the Top500 list. At that point, Tianhe-2 had slipped from 49th to 64th on the Green500. Tianhe-2 has now slipped to second place on the Top500, only surpassed by yet another new Chinese machine, NRCPC’s Sunway TaihuLight. There has also been some consolidation between the Top500 and the Green500 lists: it... » read more

Cars, Security, And HW-SW Co-Design
By Jeff Dorsch - 07 Jul, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss parallel hardware/software design with Johannes Stahl, director of product marketing, prototyping and FPGA, [getentity id="22035" e_name="Synopsys"]; [getperson id="11411" comment="Bill Neifert"], director of models technology, [getentity id="22186" comment="ARM"]; Hemant Kumar, director of ASIC design, Nvidia; and Scott Constable, senior member of ... » read more

GPUs Power Ahead
By Ann Mutschler - 05 Jul, 2016 - Comments: 0

GPUs, long a sideshow for CPUs, are suddenly the rising stars of the processor world. They are a first choice in everything from artificial intelligence systems to automotive ADAS applications and deep learning systems powered by [getkc id="261" kc_name="convolutional neural network"]. And they are still the mainstays of high-performance computing, gaming and scientific computation, to name ... » read more

CPU, GPU, or FPGA?
By Jeff Dorsch - 16 Jun, 2016 - Comments: 0

Nvidia’s new GeForce GTX 1080 gaming graphics card is a piece of work. Employing the company’s Pascal architecture and featuring chips made with a 16nm [getkc id="185" kc_name="finFET"] process, the GTX 1080’s GP104 graphics processing units boast 7.2 billion transistors, running at 1.6 GHz, and it can be overclocked to 1.733 GHz. The die size is 314 mm², 21% smaller than its GeForce ... » read more

The Secret to Reaching Rapid Verification Closure
By Ellie Burns - 16 Jun, 2016 - Comments: 0

Every design team is looking to reduce RTL verification time in order to meet aggressive schedules. Successful teams have moved their level of design abstraction up to the C++ or [gettech id="31018" comment="SystemC"] level and employ [getkc id="105" comment="high-level synthesis"] (HLS) within their design flow. By taking advantage of this high-level description, these teams also plug into int... » read more

DAC Day Three: UVM, Machine Learning And DFT Come Together
By Brian Bailey - 08 Jun, 2016 - Comments: 0

The industry and users have a love/hate relationship with UVM. It has quickly risen to become the most used verification methodology and yet at the same time it is seen as being overly complex, unwieldy and difficult to learn. The third day of DAC gets started with breakfast with Accellera to discuss UVM and what we can expect to see in the next 5 years. The discussion was led by Tom Alsop, pri... » read more

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