The Week In Review: Manufacturing

By Mark LaPedus - 08 Aug, 2014 - Comments: 0

Many are suffering from “fragiphoniphobia” without even realizing it, according to Kyocera. This is the fear of fragile phones and worries about the drops and spills ruining our smartphones and disrupting our lives. A recent survey from comScore revealed that 73% of consumers surveyed rated drop protection or scratch-proof/shatter-proof screens as the most desirable durability feature, whil... » read more

Established Nodes Getting New Attention

By Ed Sperling - 07 Aug, 2014 - Comments: 0

As the price of shrinking features increases below 28nm, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and mostly accurate analog sensors. The goals of power, performance and cost haven’t changed, but there is a growing realization among many chipmakers that the formula can be improved upon with... » read more

GPUs Dominate (Again) The Green500 List

By Barry Pangrle - 16 Jul, 2014 - Comments: 0

The Green500 has released its latest list of the top 500 most energy-efficient Supercomputers. The top 17 are heterogeneous systems (systems that use more than one type of processor), with the top 15 systems all using NVIDIA Kepler K20 GPUs paired with Intel Xeon CPUs. Still at the top of the list is the Tokyo Institute of Technology GSIC Center’s TSUBAME-KFC, an oil-cooled Kepler powered ... » read more

Five Disruptive Test Technologies

By Mark LaPedus - 19 Jun, 2014 - Comments: 0

For years, test has been a critical part of the IC manufacturing flow. Chipmakers, OSATs and the test houses buy the latest testers and design-for-test (DFT) software tools in the market and for good reason. A plethora of unwanted field returns is not acceptable in today’s market. The next wave of complex chips may require more test coverage and test times. That could translate into higher... » read more

Blog Review: June 18

By Ed Sperling - 18 Jun, 2014 - Comments: 1

Mentor’s Vern Wnek recalls “a living hell” of being trapped in a small office for three weeks with a PCB designer who ate too much garlic and sweated profusely. This could be a reality TV series. What do engineers really think about UVM? Cadence's Richard Goering braved a 7 a.m. breakfast at DAC to hear a panel of experts, including reps from Intel, Ericsson, Imagination and Freescale,... » read more

A Node By Any Other Name

By Barry Pangrle - 12 May, 2014 - Comments: 3

Have you ever wondered what gives a particular CMOS technology node its name? When we talk about 20nm, 16nm or 14nm, what exactly does that number in front of the “nm” mean anyway? Is it the first layer metal half-pitch or the gate length (and while we’re at it, is that the printed gate length, the physical gate length, or the effective gate length)? The half-pitch refers to half the m... » read more

Real Countries Have Fabs

By Ed Sperling - 17 Apr, 2014 - Comments: 3

Persistent rumblings about the sale of IBM’s semiconductor unit might have seemed absurd a couple decades ago—before IBM sold off its PC unit to Lenovo and lost the gaming chip business to AMD’s x86 chips—but no one is scoffing at the possibility these days. The reality is that IBM will never reach the volume necessary to be the No. 1 or No. 2 player in its segment. It’s not even i... » read more

Time To Revisit 2.5D And 3D

By Mark LaPedus - 17 Apr, 2014 - Comments: 2

Chipmakers are reaching various and challenging inflection points. In logic, many IC makers face a daunting transition from planar transistors at 20nm to finFETs at 14nm. And on another front, the industry is nearing the memory bandwidth wall. So perhaps it’s time to look at new alternatives. In fact, chipmakers are taking a hard look, or re-examining, one alternative—stacked 2.5D/3D chi... » read more

Blog Review: April 16

By Ed Sperling - 16 Apr, 2014 - Comments: 0

Cadence’s Richard Goering attended a workshop on “extreme” scale design automation, which looked at where else EDA tools can be used—such as intelligent traffic lights. At least there are well-defined use cases. Mentor’s Nazita Saye has compiled five predictions from the 1964 New York World’s Fair that are worth revisiting. Three of them came true. Check out the ones that didn’... » read more

Favorite Forecast Fallacies

By Barry Pangrle - 14 Apr, 2014 - Comments: 0

It’s difficult to make predictions, especially about the future. – An Old Danish Proverb. The GSA Silicon Summit was held on Thursday, April 10th at the Computer History Museum in Mountain View, CA. The opening panel session was entitled Advancements in Nanoscale Processing. The panelists were Rob Aitken (ARM), Adam Brand (Applied Materials), Peter Huang (TSMC), Nick Kepler (VLSI Researc... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?