Low-Power Architectures Go Mainstream


By Pallab Chatterjee Until recently, low power engineering has been defined by the automated use of EDA tools in the design flow to help cut back on peak dynamic power. The new generation of mobile and video products has forced a change in that methodology. There are two other fast rising architectural approaches. The first is multicore, which is prevalent in new product introductions fr... » read more

Hot Chips 2009: It’s All About Multicore And Low-Power


By Pallab Chatterjee The game has changed for processors. The goal now is data throughput, not higher gigahertz and more watts. That shift dominated the presentations at the Hot Chips conference this week. In previous years, the theme was higher single-core performance, more power and smaller geometries processes. This year it was all about multi-core and multi-power options as the realities ... » read more

First Down On The 40nm Line


The race to 40nm is over. Some chipmakers are already there, taping out designs and implementing IP that has already been qualified at the 40nm process. When exactly volume production begins and when yields improve is a matter of conjecture. TSMC so far is the only major foundry actively using the 40nm process, which is a half-node beyond 45nm. But the Common Platform already has briefed a... » read more

On, Off and Mostly Off


<p>By Ed Sperling</p> <p>System-on-chip architecture has always been about getting the most performance out of a device, and the basic premise is that when you turn on a device it is always on.</p> <p>That approach has been challenged over the past few years with a fundamental shift toward more of the design being in the ‘off’ position. Aside from reversi... » read more

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