First Down On The 40nm Line

Power issues move to center field at the next half node.


The race to 40nm is over. Some chipmakers are already there, taping out designs and implementing IP that has already been qualified at the 40nm process.

When exactly volume production begins and when yields improve is a matter of conjecture. TSMC so far is the only major foundry actively using the 40nm process, which is a half-node beyond 45nm. But the Common Platform already has briefed analysts and customers on its 40nm process, even though most of its work is at 45nm, and the Global Foundry—the AMD spinoff—has 40nm ready to go if there is customer demand.

A side benefit to consumers—and a big headache for design engineers—is that the power envelope continues to shrink with the line-widths. Low power is now standard in every design, which puts pressure on all IP vendors to create low-power versions at least concurrently with their newly qualified IP, if not first—or to make all versions low power. In the past, low-power versions typically trailed initial rollouts by 6 to 18 months.

And while that doesn’t mean all pieces of an SoC design need to be manufactured using a 40nm process—non-volatile memory, for example, is still at least a node behind—it does mean that research is well underway and on track for 32/28nm and that 40nm appears to be a relatively stable manufacturing process.

AMD, with its ATI line, and Nvidia both have 40nm versions of their latest graphics processors, which typically run at the leading edge of Moore’s Law because there is far greater potential for using more cores with existing software than many other chips. Video, in particular, is one of the easier applications to write for multiple cores because graphics rendering can be parsed into discrete units.

Low power everywhere

The power envelope in a more densely-packed piece of silicon has to be significantly lower, however. Signal integrity is a growing problem, according to design engineers, in part because of the density and the amount of current moving through the wires. Higher density also opens up real estate on a single chip for more functions that previously were on multiple chips or even multiple devices.

All of that points to lowering power wherever possible. And it means that to be successful in the market, low power design is a must. Virage Logic, which makes a variety of memory and logic IP, saw the trend clearly at 65nm when it incorporated low-power options into all of its IP instead of offering a separate low-power version.

“At 40 nanometers, if you want to create a new chip it has to be low power,” said Brani Buric, Virage’s executive vice president of marketing and sales. “We used to have high-density, high-speed and low-power versions of our IP. At 40nm, there are no separate low power products. There is a full set of low power features in both our high-density and high-speed IP, whether that’s memories or logic.”

AMD’s graphics processor group rolled out its first product at 40nm this spring. Stan Ossias, director of product management in AMD’s global/discrete graphics unit, said the bulk of the company’s work is still at 55nm and the company got a huge performance gain by re-architecting its 55nm chips.

“A lot of what we do has to do with predicting the readiness of the process at any time,” said Ossias. “We capitalize on the IP that’s available and the design he have to maximize our competitiveness. Last year, we had the choice of going to 40nm using the same architecture, but we thought we could do a better job of reaching our performance goals by redesigning the architecture. We didn’t feel the 40nm process was ready.”

That approach is one that is becoming more common among companies that typically hopped from one process node to the next in the past. The complexity of getting to the next node, along with the rising costs and uncertainties about manufacturability, yield and the IP needed in a design—not all IP available at 40nm has been proven in silicon yet—makes each new process node an increasing risk, and one that is no longer just an automatic decision.

At least part of the risk assessment also has to do with power consumption. Each new node also requires reducing the power consumption, which involves a litany of design tricks ranging from power gating for active power to utilizing power islands for static leakage, different gate structures and a variety of exotic insulation materials.

“Power is one of the fundamental areas we think about with technology evolution,” said Ossias. “Every time we shrink the process, we have to put more and more effort into decreasing power. That involves not just the individual device, but how that device interoperates with other devices. It’s a big consideration.”

40 vs. 45nm

Even moving from 45nm to 40nm is raising some questions. The foundry business is extremely competitive and having the next process used to be a competitive advantage, but so far only TSMC is actively pushing 40nm. The foundry told analysts that it opted for 40nm instead of 45nm because the process could be tuned better for device performance.

Joanne Itow, managing director of manufacturing at Semico Research, said the number of half nodes is exploding. She said that gives both foundries and companies a chance to firm up the processes and move more gradually to the next full node. The Common Platform, for example, is working on 28nm, which is the half node between 32nm and 22nm.

Global Foundries, which is the AMD spinoff, will work with customers for a specific implementation at 40nm or refine its bulk 45nm process, according to spokesman Jon Carvill. But he said the next step under development is a 32nm and 28nm bulk CMOS process.

Still, now that the foundries have reached the node and are working on the next one, the question remains of just how many chipmakers will move to the next half node and how quickly. There is a lot of conjecture now that the pieces are falling into place for 40nm production, but so far there are no definitive answers.

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