Who’s Winning The FinFET Foundry Race?

By Mark LaPedus - 14 Aug, 2014 - Comments: 5

The leading-edge foundry business is challenging. For starters, foundry vendors require vast resources, gigantic fabs and lots of know-how. And yet, it’s still difficult to make money in this business. That has certainly proven to be the case in the planar transistor era, but the challenges and costs are escalating as foundry vendors begin to ramp up finFET technologies at the 16nm/14nm no... » read more

Real Countries Have Fabs

By Ed Sperling - 17 Apr, 2014 - Comments: 3

Persistent rumblings about the sale of IBM’s semiconductor unit might have seemed absurd a couple decades ago—before IBM sold off its PC unit to Lenovo and lost the gaming chip business to AMD’s x86 chips—but no one is scoffing at the possibility these days. The reality is that IBM will never reach the volume necessary to be the No. 1 or No. 2 player in its segment. It’s not even i... » read more

Accelerating Moore’s Law

By Ed Sperling - 21 Feb, 2013 - Comments: 0

By Ed Sperling Ever since the inception of Moore’s Law, process nodes have moved forward at a rate of once every 18 to 24 months. Companies have been talking about slowing down the rate of progression as things get harder, but at least for the next couple of process nodes something very strange will occur—Moore’s Law will accelerate. The root cause is growing competition for a shrinki... » read more

The Best Foundry Strategy

By Joanne Itow - 21 Feb, 2013 - Comments: 0

By Joanne Itow Today, foundries supply more than 20% of the silicon used to produce all the semiconductor products sold. The foundry impact has grown from only 10% in 1997 to 24% today. The significance of foundries is even more evident when focused on logic wafers alone. Figure 1. Foundry Wafers as a Percent of Total, IC’s, and IC’s Minus Memory [caption id="attachment_7339" align="... » read more

Making The Right Choices

By Ed Sperling - 21 Feb, 2013 - Comments: 0

FD-SOI at 28nm, or finFETs at 20/14nm? To companies looking at the cost equation, the total market opportunity for SoCs and the NRE required to get there, this is still a manageable formula. It requires lots of number crunching and some unknowns, but by the time you get done with the math it still falls within an acceptable margin of error and the choices are relatively simple. For foundries... » read more

Tech Talk: Getting To The Next Node

By Ed Sperling - 14 Feb, 2013 - Comments: 0

IBM's Gary Patton talks with Low-Power/High-Performance Engineering about finFETs, EUV, and the challenges of staying on the Moore's Law road map. [youtube vid=jtz9XSXyBp0] » read more

High Performance And Low Power

By Ed Sperling - 14 Apr, 2011 - Comments: 0

By Pallab Chatterjee As mobile platforms become a larger part of the component spectrum, their need for optimization beyond low power has moved to the forefront. Traditionally, standard "line-cord" based products in both the consumer and commercial sectors have used the "G" label processes from semiconductor foundries. These processes had the highest-yielding combination of design rules, d... » read more

Power Optimization Below 28nm

By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Pallab Chatterjee Process scaling has normally been performed on a lithographic basis, but as processes dip below 32nm there are optimization options beyond the lithographic and area reduction. The Common Platform Group and GlobalFoundries have added the tradeoffs of power and performance optimization in addition to area in their 28nm flows. TSMC uses a five-way optimization that also h... » read more

Pricey Processes For Low Power

By Ed Sperling - 08 Apr, 2010 - Comments: 0

By Pallab Chatterjee Recently Samsung gave an update on the status and availability of its advanced 32/28nm process technology for use in foundry. The process is targeted for shipping designs to customers at the end of this year, with a road map that continues through the 22/20nm nodes and down to 15nm. What was particularly interesting were several key innovations that have made this all p... » read more

Who’s In Control Now?

By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Power is shifting across the design industry in multiple ways and sometimes across multiple continents, driven by complexity and cost pressures and entirely new forms of competition. On one side of the equation, foundries are dictating more of what goes on up front in the design cycle. Design for manufacturing is a prerequisite at 45nm and below, and they’re the ones dictatin... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

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