Power Optimization Below 28nm

Tradeoffs for power, performance have been added to area at 28nm with high k/metal gate technology

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By Pallab Chatterjee
Process scaling has normally been performed on a lithographic basis, but as processes dip below 32nm there are optimization options beyond the lithographic and area reduction.

The Common Platform Group and GlobalFoundries have added the tradeoffs of power and performance optimization in addition to area in their 28nm flows. TSMC uses a five-way optimization that also has area, power and performance as three of the points.

The enabler of HKMG (high k/metal gate) is the process enhancement that allows power optimization to take place. The process nodes of 90nm, 65nm, and 4Xnm were plagued with device leakage issues. These leakage issues create a pause in the operating voltage scaling of the circuits at 1.2-1.3v. The use of HKMG, in either a GF (gate first) or GL (gate last) process flow, allows for a primary reduction of the device leakage. The corresponding benefit of the reduced leakage is the ability to vary the threshold voltage (Vt) of both the P and N transistors, in the case of GlobalFoundries over a range of 300mv at 28nm. Since the Vt can be adjusted without corrupting the basic device operation, the operating voltage can be reduced while delivering the same device switching characteristics.

Both the GF and GL versions of the HKMG process support a standard “G” style logic optimized flow, an “LP” low-power optimized flow and an “HP” high-performance optimized flow. As the reduced process size can be multi-point optimized, it is possible to create a 28nm process that provides 2x the performance (freq*density) at the same power factor as a 40nm node. Additionally, a low-power optimization supports a 28nm process at 1.1v, producing a 49% increase in operating frequency while having a simultaneous 44% reduction in switching power.

The ability to now scale the Vt of the small devices and reduce the power supply gives new design flexibility at the 2Xnm nodes. The 28nm and 22nm flows can support multiple Vts in a single design and, correspondingly, different power supply levels in isolated islands. This level of control over the devices is reminiscent of the capabilities last seen in the 250nm+ nodes. Designers now can perform IP and cell level optimization for power and area based on design rule adjustments and device selection. For IP, differentiation in the rules can optimize SRAM, logic and analog/RF all with different Vts and operating voltages. This makes the block and SoC-level design power and performance optimized only if the design flow supports technology based optimization.

Most design flows for low power rely on gate power switching and a single Vt selection per block The 28nm flows have context sensitivity for all the physical design components. With the use of computational lithography solutions, and the symmetry requirements of double patterning, multiple sets of design rules are used to drive the function optimization. The support environment allows for multiple SRAM types (operating voltages, Vt, density, speed, etc.) to be built and dropped into blocks that may share a common power-gating control. In the 40nm to 90nm designs, these variations could not be combined.

The very small cell size and device pitch in 28nm and 22nm processes has created a need for new interconnect solutions. These new interconnect methods are needed to ensure the low power operation of the designs, as the interconnect is a major consumer of the device power. Most of the designs in these nodes utilize bump and in-die pads. At the 250nm through 45nm nodes, the bond pad size for bump bonds are still the traditional 110um size on a 150um pitch. At the 28nm and 22nm nodes, the bump bonds can be reduced to a 60um size on a 100um pitch. This reduction in size creates a minimized interconnect path for both power and signals, and drive the area based optimization aspects of the process.

Low power design in the 2Xnm nodes is now a full design/technology/lithography co-optimization task. The design workflows have to address both device characteristics and lithography variability to ensure any power factor design goals.