Who’s In Control Now?

Getting chips out the door at the next process node is wreaking havoc on the design industry’s political structure.


By Ed Sperling

Power is shifting across the design industry in multiple ways and sometimes across multiple continents, driven by complexity and cost pressures and entirely new forms of competition.

On one side of the equation, foundries are dictating more of what goes on up front in the design cycle. Design for manufacturing is a prerequisite at 45nm and below, and they’re the ones dictating the rules. Moreover, those rules are becoming far more stringent at 32/28nm because the lasers used to etch chips aren’t thin enough at 193nm—even with immersion technology—to etch all the polygons as irregularly as in the past.

On the other side, ESL modeling is removing much of the control for designs from individual design engineers used to working with RTL or various levels above that. Interfaces are entirely too complex to map out by hand, IP is bought by the block with the real challenge moving to the integration and testing of those blocks, and verification continues to become more unwieldy as tradeoffs between performance, area and power—and power in multiple states and islands—become orders of magnitude more complex.

The foundry shift

With new fabs costing $4 billion to $5 billion for the most advanced process nodes, it’s no wonder that most companies no longer can afford them. Even IBM has partners for developing new processes, and it continues to expand its ecosystem for new technologies to include companies like Sony, Infineon and AMD. And the mighty Intel, until recently the one holdout in the integrated-device manufacturing model, has shifted manufacturing for its Atom chip to TSMC.

But that shift also has concentrated an increasing amount of power in the hands of a few foundries, most notably TSMC, UMC and the Common Platform triumvirate of IBM, Samsung and Chartered Semiconductor. With cost pressures rising on them, they’re in a position to both dictate what gets built, how it gets built, and what gets used in a design.

Already, the foundries are dictating what IP gets validated. Tom Quan, TSMC deputy director, said the foundry has a portfolio of IP companies as a necessary part of getting designs into production.

“We’ve got to understand who’s doing what, who’s got the star IP,” said Quan. “We have to know all the pieces and pick the right players. We also have to look at the emerging players and choose which ones we think are the most promising. We’re betting on them.”

This becomes particularly important at future nodes. Currently, about two-thirds of TSMC’s revenue comes from the 65nm and 90nm process nodes. In the first half of 2010, the foundry estimates that half its revenue will come from 28nm chips.

That also means more restrictive design rules, because if the designs don’t head into production then the foundries don’t make money.

“Restrictive rules increase productivity,” said Quan. “At 40nm, we had some rules. At 28nm, there will be more. And at 22nm, there will be even more.”

Driving those rules are layout-dependent effects caused by everything from diffusion to stress engineering. Those effects can be theorized, but reality isn’t always the same. And that means the layout designer will have far less freedom than in the past.

That’s no surprise to some long-time industry investors. Startup Tela Innovations—notably funded by Cadence, Qualcomm and Intel, among others—is focused on developing more regular layouts to make them easier to print. Neil Carney, VP of marketing at Tela, said the company’s focus is on front-end rules, including ways to break designs into to parts using double patterning.

One source, who spoke on condition that he not be named, said the new design rules put designers back 20 years. “What you’re giving up is shape-based technology where you tune with wires and vias,” he said. “At 22nm, you’re back on the grid. Wrong-way wires will disappear.”

That opinion was echoed by Giuseppe Forniciari, senior design manager at ST Microelectronics: “At 40nm and below, wiring dominates gates and margins add too much power.” He said the need for concurrent multi-corner, multi-mode throughput on the flow is now essential.

Raising the abstraction level

While EDA executives jab at the growing control of the foundries whenever the opportunity arises, individual designers are taking shots at the growing control of the large EDA vendors. ESL modeling removes much of the control in a design from their hands and raises it to a level that makes them more reliant on tools than ever before.

This is, in part, why analog engineers have so strongly resisted using EDA tools. It’s also why modeling has experienced relatively slow growth in the digital world. But with complexity now beyond the comprehension of the human brain—particularly within the time constraints of most chipmakers—raising up the level of abstraction and keeping track of all these different levels, power states and voltage islands makes modeling a necessity.

Modeling plays neatly into the hands of the big EDA vendors, which are working on everything from simulation to validation and software prototyping. Tadahiko Yamamoto, chief specialist in Toshiba’s design methodology development group, said that with Synopsys’ IC Validation Design rule checker it was able to reduce the number of steps to three from what was previously six. In addition, total time spent was reduced to a few hours instead of more than a day.

Intel is even starting to measure progress in “time to model.” Daniel Pace, senior software engineer at Intel, said the goal is quick turnaround for adjusting the model and mixed levels of abstraction.


Complexity, technology limitations in areas such as lithography, time-to-market pressures and the rising cost of getting chips out the door will change fundamental power relationships within the semiconductor design industry. Systems on chip require different skill sets than simple IC designs, but SoCs built at 22nm will require different skills, tools, packaging and possibly even different substrates and materials than those built at 28nm. So far, no one is even sure what the half node beyond 22nm will be or what that will entail.

Chipmakers are coping with all of this by outsourcing designs altogether to companies like eSilicon or Open Silicon, skipping nodes, or hanging back a node or two on some products to save development time and cost because manufacturing processes are more mature there. It’s even too expensive to continue developing their own point tools at the leading edge of design, which used to be a differentiator for many IDMs—back when there were IDMs—and putting more resources into software development.

But if these kinds of changes in the industry’s power structure are happening over the course of a couple of process nodes, what will happen at the next couple of nodes beyond 22nm?