Making The Right Choices

While chipmakers usually can decide what makes sense for their markets, it’s a lot tougher for foundries and EDA companies.


FD-SOI at 28nm, or finFETs at 20/14nm? To companies looking at the cost equation, the total market opportunity for SoCs and the NRE required to get there, this is still a manageable formula. It requires lots of number crunching and some unknowns, but by the time you get done with the math it still falls within an acceptable margin of error and the choices are relatively simple.

For foundries, the makers of EDA tools, and even IP vendors, there is no such accepted distribution to fall back on. For one thing, many decisions have to be made well in advance of the market. If there is no process at 14nm, there are no 14nm chips.

Good forecasting has always been critical to the foundry model, but it is becoming critical to the entire ecosystem. What happens, for example, when delivery schedules of key pieces go astray? EUV was supposed to have been ready several process nodes ago, and it still isn’t ready—despite billions of dollars of research and the best minds in process technology and physics trying to get the power source to the point of commercial viability. How do you plan for that? Answer: You can’t.

And how do you plan for eletromigration causing bigger problems than anyone expected, or a shortage of some key materials caused by geopolitical crises? How do you know black-box IP will work as planned next to other black-box IP? And even worse, how do you plan for your competitors leapfrogging you because you didn’t think the technology was worth investing in, or at least investing on a certain timetable?

FD-SOI is a case in point. Will there be enough big customers to warrant the investment made by the Common Platform companies? At this point the answer appears to be yes, but can companies like TSMC and UMC squeak by focusing on finFETs instead? Or will they ultimately need both finFETs and EUV? And by that time, where will stacked die be?

Timing is everything in business, but at 14nm and 10nm a timing error could cost tens of billions of dollars. It’s turned into a high-stakes poker game, where everyone is all-in all the time. What’s different this time, though, is that going all-in requires a commitment by the entire ecosystem, from DFM, DFT, DFY tools vendors to substrate suppliers, packaging houses and foundries. This is a team effort, but every member of the team has to excel for it to work. And given the growing list of challenges, timing will be much harder to guarantee in the future—and so will the choices companies have to make.