Joe Costello To Get Back Into EDA?

By Brian Bailey - 31 Dec, 2013 - Comments: 3

While other writers in this world rely on gossip, there is a lot more that can come from hard work and paying attention. Perhaps one of the most famous and charismatic people from the EDA world is [getperson id="11147" p_name="Joe Costello"] – former CEO of [getentity id="22032" e_name="Cadence"] and still missed by many. Until recently he was CEO of a company called Orb Networks, a streamin... » read more

Still Room For Startups?

By Ed Sperling - 25 Feb, 2010 - Comments: 0

Can startups still survive in an increasingly complex, high up-front investment world? System-Level Design posed that question to Mentor Graphics, Synopsys, Oasys and an end user. [youtube vid=3RGvRnDGiTE] » read more

Remaking The Design Landscape

By Ed Sperling - 28 Jan, 2010 - Comments: 0

By Ed Sperling Every now and then a new trend comes along in the semiconductor design world, often because an old tool doesn’t work well anymore or because a new one is achieving critical mass. Lithography moved to immersion when the wavelength couldn’t be refracted far enough anymore. Designers at the advanced end of Moore’s Law began using tools like high-level synthesis and Transa... » read more

Synthesis: Next Steps In SoC Design

By Ed Sperling - 17 Dec, 2009 - Comments: 0

Five experts sound off to System-Level Design on the state of synthesis and what's needed in the future: Shawn McCloud, product line director for Catapult C Synthesis at Mentor Graphics; Chris Eddington, director of marketing for system-lvel products at Synopsys; Brett Cline, VP of marketing at Forte Design Systems; Andy Biddle, director of business development at Magma and Sanjiv Kaul, executi... » read more

Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Oasys

Joe Costello To Get Back Into EDA?

Still Room For Startups?

Remaking The Design Landscape

Synthesis: Next Steps In SoC Design

Trending Articles

Hybrid Bonding Makes Strides Toward Manufacturability

Americas Chip Funding Energizes Industry

Advanced Packaging Driving New Collaboration Across Supply Chain

Startup Funding: Q3 2024

Chiplets Make Progress Using Interconnects As Glue

Knowledge Centers
Entities, people and technologies explored