tag: Onto Innovation

Systematic Yield Issues Now Top Priority At Advanced Nodes
By Laura Peters - 06 Dec, 2022 - Comments: 0

Systematic yield issues are supplanting random defects as the dominant concern in semiconductor manufacturing at the most advanced process nodes, requiring more time, effort, and cost to achieve sufficient yield. Yield is the ultimate hush hush topic in semiconductor manufacturing, but it's also the most critical because it determines how many chips can be profitably sold. "At older nodes, b... » read more

Adopting Predictive Maintenance On Fab Tools
By Anne Meixner - 06 Dec, 2022 - Comments: 0

Predictive maintenance, based on more and better sensor data from semiconductor manufacturing equipment, can reduce downtime in the fab and ultimately cut costs compared with regularly scheduled maintenance. But implementing this approach is non-trivial, and it can be disruptive to well-honed processes and flows. Not performing maintenance quickly enough can result in damage to wafers or the... » read more

Metrology Sampling Plans Are Key For Device Analytics And Traceability
By Mike McIntyre - 06 Dec, 2022 - Comments: 0

A mother steps on the brakes, bringing her car to a stop as she drops her kids off for dance lessons. At the time, she doesn't notice anything wrong, but when she takes her car in for its regular service appointment, the mechanic conducts a diagnostic check and discovers that the primary brake system on the car had failed because of a faulty braking controller without anyone realizing it. Fortu... » read more

Next Steps For Improving Yield
By Laura Peters - 08 Nov, 2022 - Comments: 0

Chipmakers are ramping new tools and methodologies to achieve sufficient yield faster, despite smaller device dimensions, a growing number of systematic defects, immense data volumes, and massive competitive pressure. Whether a 3nm process is ramping, or a 28nm process is being tuned, the focus is on reducing defectivity. The challenge is to rapidly identify indicators that can improve yield... » read more

Heterogeneous Integration: Correcting Overlay Errors On Advanced Integrated Circuit Substrates (AICS)
By John Chang - 08 Nov, 2022 - Comments: 0

By John Chang, with Corey Shay, James Webb, and Timothy Chang For high-performance computing, artificial intelligence, and data centers, the path ahead is certain, but with it comes a change in substrate format and processing requirements. Instead of relying on the quest for the next technology node to bring about future device performance gains, manufacturers are charting a future based inc... » read more

Legacy Tools, New Tricks: Optical 3D Inspection
By Karen Heyman - 08 Nov, 2022 - Comments: 0

Stacking chips is making it far more difficult to find existing and latent defects, and to check for things like die shift, leftover particles from other processes, co-planarity of bumps, and adhesion of different materials such as dielectrics. There are several main problems: Not everything is visible from a single angle, particularly when vertical structures are used; Various struc... » read more

Test Connections Clean Up With Real-Time Maintenance
By Anne Meixner - 08 Nov, 2022 - Comments: 0

Test facilities are beginning to implement real-time maintenance, rather than scheduled maintenance, to reduce manufacturing costs and boost product yield. Adaptive cleaning of probe needles and test sockets can extend equipment lifetimes and reduce yield excursions. The same is true for load board repair, which is moving toward predictive maintenance. But this change is much more complicate... » read more

Yield Is Top Issue For MicroLEDs
By Laura Peters - 11 Oct, 2022 - Comments: 0

MicroLED display makers are marching toward commercialization, with products such as Samsung’s The Wall TV and Apple’s smart watch expected to be in volume production next year or in 2024. These tiny illuminators are the hot new technology in the display world, enabling higher pixel density, better contrast, lower power consumption, and higher luminance in direct sunlight — while consu... » read more

Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues
By Karen Heyman - 11 Oct, 2022 - Comments: 0

Bumps are a key component in many advanced packages, but at nanoscale levels making sure all those bumps have a consistent height is an increasing challenge. Without co-planarity, surfaces may not properly adhere. That can reduce yield if the problem is not identified in packaging, or it can cause reliability problems in the field. Identifying those issues requires a variety of process steps... » read more

Heterogeneous Integration: Exposing Large Panels With Fewer Shots
By John Chang - 11 Oct, 2022 - Comments: 0

By John Chang, with Corey Shay, James Webb, and Timothy Chang The More than Moore era is upon us, as manufacturers increasingly turn to back-end advances to meet the next-generation device performance gains of today and tomorrow. In the advanced packaging space, heterogeneous integration is one tool helping accomplish these gains by combining multiple silicon nodes and designs inside one pac... » read more

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