tag: Open-Silicon

Experts At The Table: Multi-Core And Many-Core
By Ed Sperling - 29 Jul, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Naveed Sherwani, CEO of Open-Silicon; Amit Rohatgi, principal mobile architect at MIPS; Grant Martin, chief scientist at Tensilica; Bill Neifert, CTO at Carbon Design Systems; and Kevin McDermott, director of market development for ARM’s System Design Division. What follows are excerpts of that conversation. LPE: Is software taking advan... » read more

Solving Memory Subsystem Bottlenecks In 3D Stacks
By Ann Mutschler - 28 Jul, 2011 - Comments: 0

In today’s do-or-die market environment, many SOC makers strive to differentiate their product based upon the rate at which it performs processing. Closely coupled are power concerns that have led to dominance of a multi-core approach, while economic considerations have resulted in the dominance of the Unified Memory Architecture, where all the processors share access to external DRAM. Stacki... » read more

Experts At The Table: Multi-Core And Many-Core
By Ed Sperling - 21 Jul, 2011 - Comments: 0

By Ed Sperling Low-Power Engineering sat down with Naveed Sherwani, CEO of Open-Silicon; Amit Rohatgi, principal mobile architect at MIPS; Grant Martin, chief scientist at Tensilica; Bill Neifert, CTO at Carbon Design Systems; and Kevin McDermott, director of market development for ARM’s System Design Division. What follows are excerpts of that conversation. LPE: Computers aren’t gettin... » read more

SoC Design In 5 Years
By Ed Sperling - 30 Jun, 2011 - Comments: 0

By Ed Sperling The semiconductor industry is used to looking at changes every couple of years, based upon the progression of Moore’s Law. But look out further, over the next five years when the most advanced process node is somewhere between 14nm and 16nm, and the job of designing and manufacturing an SoC will look very different. At the center of this change are three very significant tr... » read more

Executive Briefing: Naveed Sherwani
By Ed Sperling - 06 Jun, 2011 - Comments: 0

Open-Silicon's CEO talks with System-Level Design about getting the business priorities of designing a complex SoC in line with the technology; why getting chips out the door on time is critical and why it's not happening. [youtube vid=OAQ9JxJKYHU] » read more

Who’s In Control?
By Ed Sperling - 26 May, 2011 - Comments: 0

By Ed Sperling A power shift is under way across the SoC world that ultimately determine who wins the business, who gets the biggest share and what technologies are ultimately used to get there. Complexity has reached a point where being able to pull the necessary pieces from a disaggregated supply chain is becoming much more difficult. That helps explain why all three of the major EDA comp... » read more

SoC Ecosystems Become More Tightly Integrated
By Ed Sperling - 28 Apr, 2011 - Comments: 0

By Ed Sperling SoC ecosystems are changing. Quality and focus are replacing volumes of names as companies that fund them begin to narrow down which partners add the most value and which markets they need to target. Establishing a ring of allies is nothing new, of course. IBM had its circle of most trusted software partners back in the 1970s when mainframes were the dominant computing platfo... » read more

The Quest For A Better IP Integration Methodology
By Ed Sperling - 31 Mar, 2011 - Comments: 0

By Ed Sperling With the amount of IP in SoC designs now hitting an estimated 70% to 90%, companies are scrambling to figure out a way to more consistently integrate that IP and to test that it will work as expected. This is easier said than done, however, for a number of reasons: There are numerous types of IP, ranging from I/O to logic and memory. Not all IP is of equal quality. ... » read more

Remaking The Design Landscape
By Ed Sperling - 28 Jan, 2010 - Comments: 0

By Ed Sperling Every now and then a new trend comes along in the semiconductor design world, often because an old tool doesn’t work well anymore or because a new one is achieving critical mass. Lithography moved to immersion when the wavelength couldn’t be refracted far enough anymore. Designers at the advanced end of Moore’s Law began using tools like high-level synthesis and Transa... » read more

Verifying Low-Power Designs
By Ed Sperling - 14 Jan, 2010 - Comments: 0

By Ed Sperling Power islands and multiple voltages used to be reserved for cell phone and process companies, but as more companies move to 65nm and 45nm process nodes these approaches to saving power—particularly in chips with multiple cores—are becoming mainstream. The problem isn’t in the architecture of the chips, although that certainly brings its own set of challenges. More and m... » read more

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